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/linux/tools/lib/
H A Dlist_sort.c8 * Returns a list organized in an intermediate format suited
12 __attribute__((nonnull(2,3,4)))
14 struct list_head *a, struct list_head *b) in merge() argument
19 /* if equal, take 'a' -- important for sort stability */ in merge()
20 if (cmp(priv, a, b) <= 0) { in merge()
21 *tail = a; in merge()
22 tail = &a->next; in merge()
23 a = a->next; in merge()
24 if (!a) { in merge()
50 merge_final(void * priv,list_cmp_func_t cmp,struct list_head * head,struct list_head * a,struct list_head * b) merge_final() argument
210 struct list_head *a = *tail, *b = a->prev; list_sort() local
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/linux/lib/
H A Dlist_sort.c8 * Returns a list organized in an intermediate format suited
12 __attribute__((nonnull(2,3,4)))
14 struct list_head *a, struct list_head *b) in merge() argument
19 /* if equal, take 'a' -- important for sort stability */ in merge()
20 if (cmp(priv, a, b) <= 0) { in merge()
21 *tail = a; in merge()
22 tail = &a->next; in merge()
23 a = a->next; in merge()
24 if (!a) { in merge()
50 merge_final(void * priv,list_cmp_func_t cmp,struct list_head * head,struct list_head * a,struct list_head * b) merge_final() argument
227 struct list_head *a = *tail, *b = a->prev; list_sort() local
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/linux/arch/powerpc/crypto/
H A Dmd5-asm.S61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
69 add a,a,rT0; /* 1: a = a + f */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
72 add a,a,w0; /* 1: a = a
85 R_16_31(a,b,c,d,w0,w1,p,q,k0h,k0l,k1h,k1l) global() argument
105 R_32_47(a,b,c,d,w0,w1,p,q,k0h,k0l,k1h,k1l) global() argument
122 R_48_63(a,b,c,d,w0,w1,p,q,k0h,k0l,k1h,k1l) global() argument
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/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
13 "Counter": "0,1,2,3",
21 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
22 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 "BriefDescription": "Load miss in all TLB levels causes a pag
20 { global() object
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
13 "Counter": "0,1,2,3",
21 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
22 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 "BriefDescription": "Load miss in all TLB levels causes a pag
20 { global() object
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/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
13 "Counter": "0,1,2,3",
21 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
22 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 "BriefDescription": "Load miss in all TLB levels causes a pag
20 { global() object
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/linux/lib/crypto/x86/
H A Dsha256-ssse3-asm.S11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
91 INP = %rsi # 2nd arg
99 a = %eax define
134 # Rotate values of symbols a...h
143 b = a
144 a = TMP_ define
148 ## compute s0 four at a time and s1 two at a tim
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H A Dsha256-avx-asm.S11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
98 INP = %rsi # 2nd arg
106 a = %eax define
140 # Rotate values of symbols a...h
149 b = a
150 a = TMP_ define
154 ## compute s0 four at a tim
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/linux/arch/sparc/include/asm/
H A Dopcodes.h18 #define CRC32C(a,b,c) \ argument
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
30 #define AES_EROUND01(a,b,c,d) \ argument
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
32 #define AES_EROUND23(a,b,c,d) \ argument
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
34 #define AES_DROUND01(a, argument
36 AES_DROUND23(a,b,c,d) global() argument
38 AES_EROUND01_L(a,b,c,d) global() argument
40 AES_EROUND23_L(a,b,c,d) global() argument
42 AES_DROUND01_L(a,b,c,d) global() argument
44 AES_DROUND23_L(a,b,c,d) global() argument
46 AES_KEXPAND1(a,b,c,d) global() argument
48 AES_KEXPAND0(a,b,c) global() argument
50 AES_KEXPAND2(a,b,c) global() argument
53 DES_IP(a,b) global() argument
55 DES_IIP(a,b) global() argument
57 DES_KEXPAND(a,b,c) global() argument
59 DES_ROUND(a,b,c,d) global() argument
62 CAMELLIA_F(a,b,c,d) global() argument
64 CAMELLIA_FL(a,b,c) global() argument
66 CAMELLIA_FLI(a,b,c) global() argument
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/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dvirtual-memory.json3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
22 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
23 "Counter": "0,1,2,3",
27 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a deman
21 { global() object
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/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
23 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a deman
21 { global() object
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/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
23 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a deman
21 { global() object
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/linux/drivers/input/serio/
H A DKconfig11 * standard AT keyboard and PS/2 mouse *
17 To compile this driver as a module, choose M here: the
24 the architecture might use a PC serio device (i8042) to
34 i8042 is the chip over which the standard AT keyboard and PS/2
40 To compile this driver as a module, choose M here: the
55 To compile this driver as a module, choose M here: the
62 Say Y here if you have a Texas Instruments TravelMate notebook
63 equipped with the ct82c710 chip and want to use a mouse connected
68 To compile this driver as a module, choose M here: the
79 Say Y here if you built a simpl
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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/
H A Dl2_cache.json4 "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache."
8 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
12 "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line."
16 "PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the level 2 data or unified cache."
20 "PublicDescription": "Counts accesses to the level 2 cach
10 { global() object
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/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A Dvirtual-memory.json3 "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.",
4 "Counter": "0,1,2,3,4,5,6,7",
12 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTL
20 { global() object
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json117 "PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented",
120 "BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluste
8 { global() object
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/linux/drivers/input/mouse/
H A DKconfig9 Say Y here, and a list of supported mice will be displayed.
17 tristate "PS/2 mouse"
24 Say Y here if you have a PS/2 mouse connected to your system. This
25 includes the standard 2 or 3-button PS/2 mouse, as well as PS/2
30 in a specialized Xorg/XFree86 driver at:
32 and a new version of GPM at:
39 To compile this driver as a modul
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/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
23 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
31 "BriefDescription": "Page walks completed due to a deman
21 { global() object
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/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
23 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
31 "BriefDescription": "Page walks completed due to a deman
21 { global() object
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/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
22 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
23 "Counter": "0,1,2,3",
26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
31 "BriefDescription": "Page walks completed due to a deman
21 { global() object
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/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Ddevlink_trap_control.sh15 # | | default via 2001:db8:1::2 |
22 # | 2001:db8:1::2/64 |
24 # | 2001:db8:2::2/64 |
32 # | | default via 2001:db8:2::2 |
34 # | | 2001:db8:2::1/64 |
98 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
103 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
111 simple_if_init $h2 198.51.100.1/24 2001:db8:2
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/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A Dvirtual-memory.json3 "BriefDescription": "Page walk completed due to a demand load to a 1GB page",
4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.",
12 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a pag
20 { global() object
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/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-rgb.rst9 These formats encode each pixel as a triplet of RGB values. They are packed
12 bits required to store a pixel is not aligned to a byte boundary, the data is
20 or a permutation thereof, collectively referred to as alpha formats) depend on
24 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
25 but can set the alpha bit to a user-configurable value, the
28 the value specified by that control. Otherwise a corresponding format without
34 filled with meaningful values by applications. Otherwise a corresponding format
38 Formats that contain padding bits are named XRGB (or a permutation thereof).
44 - In all the tables that follow, bit 7 is the most significant bit in a byt
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/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dvirtual-memory.json3 "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.",
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a deman
20 { global() object
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/linux/Documentation/filesystems/
H A Dconfigfs.rst16 configfs is a ram-based filesystem that provides the converse of
17 sysfs's functionality. Where sysfs is a filesystem-based view of
18 kernel objects, configfs is a filesystem-based manager of kernel
21 With sysfs, an object is created in kernel (for example, when a device
24 readdir(3)/read(2). It may allow some attributes to be modified via
25 write(2). The important point is that the object is created and
27 representation, and sysfs is merely a window on all this.
29 A configfs config_item is created via an explicit userspace operation:
30 mkdir(2). It is destroyed via rmdir(2)
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