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/linux/drivers/video/fbdev/
H A Dcontrolfb.h42 /* Vertical parameters are in units of 1/2 scan line */
51 /* Horizontal params are in units of 2 pixels */
52 struct preg hperiod; /* horiz period - 2 */
74 /* Vertical parameters are in units of 1/2 scan line */
83 /* Horizontal params are in units of 2 pixels */
85 unsigned hperiod; /* horiz period - 2 */
97 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
113 int m[2]; /* 0: 2MB vram, 1: 4MB vram */
120 {{-1,-1}}, /* 512x384, 60Hz interlaced (NTSC) */
121 {{-1,-1}}, /* 512x384, 60Hz */
[all …]
H A Dmacmodes.h21 #define VMODE_512_384_60I 1 /* 512x384, 60Hz interlaced (NTSC) */
22 #define VMODE_512_384_60 2 /* 512x384, 60Hz */
23 #define VMODE_640_480_50I 3 /* 640x480, 50Hz interlaced (PAL) */
24 #define VMODE_640_480_60I 4 /* 640x480, 60Hz interlaced (NTSC) */
25 #define VMODE_640_480_60 5 /* 640x480, 60Hz (VGA) */
26 #define VMODE_640_480_67 6 /* 640x480, 67Hz */
27 #define VMODE_640_870_75P 7 /* 640x870, 75Hz (portrait) */
28 #define VMODE_768_576_50I 8 /* 768x576, 50Hz (PAL full frame) */
29 #define VMODE_800_600_56 9 /* 800x600, 56Hz */
30 #define VMODE_800_600_60 10 /* 800x600, 60Hz */
[all …]
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
84 int pitch[2]; /* bytes/line, indexed by color_mode */
90 /* Register values for 1024x768, 75Hz mode (17) */
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
107 /* Register values for 1024x768, 72Hz mode (15) */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
114 * Yes, even though MacOS calls it "72Hz", in reality it's about 70Hz.
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
126 /* Register values for 1024x768, 60Hz mode (14) */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
[all …]
/linux/kernel/time/
H A Dtimeconst.bc17 return (2^b*n+d-1)/d;
25 v = 2^b*(d-1)/d;
30 which brings the mul value into the range 2^b-1 <= x < 2^b. Such
37 if (m >= 2^(b-1))
43 define timeconst(hz) {
45 print "/* Time conversion constants for HZ == ", hz, " */\n"
54 print "#if HZ != ", hz, "\n"
55 print "#error \qinclude/generated/timeconst.h has the wrong HZ value!\q\n"
58 if (hz < 2) {
59 print "#error Totally bogus HZ value!\n"
[all …]
/linux/arch/riscv/lib/
H A Ddelay.c24 * jiffies_per_sec = HZ
27 * Therefore the constant part is HZ / 1000000 which is a small
29 * scale up this constant by 2^31, perform the actual multiplication,
30 * and scale the result back down by 2^31 with a simple shift:
36 * UDELAY_MULT = 2^31 * HZ / 1000000
37 * = (2^31 / 1000000) * HZ
38 * = 2147.483648 * HZ
39 * = 2147 * HZ + 483648 * HZ / 1000000
42 * delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000.
46 #define UDELAY_MULT (2147UL * HZ + 483648UL * HZ / 1000000UL)
[all …]
/linux/drivers/iio/accel/
H A Dst_accel_core.c31 #define ST_ACCEL_FS_AVL_2G 2
118 [2] = LSM330D_ACCEL_DEV_NAME,
130 { .hz = 1, .value = 0x01, },
131 { .hz = 10, .value = 0x02, },
132 { .hz = 25, .value = 0x03, },
133 { .hz = 50, .value = 0x04, },
134 { .hz = 100, .value = 0x05, },
135 { .hz = 200, .value = 0x06, },
136 { .hz = 400, .value = 0x07, },
137 { .hz = 1600, .value = 0x08, },
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
14 # Scan Frequency 31.469 kHz 59.94 Hz
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
[all …]
/linux/drivers/gpu/drm/ast/
H A Dast_vbios.c30 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60 Hz */
32 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72 Hz */
33 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2e },
34 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75 Hz */
36 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85 Hz */
42 { 1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56 Hz */
44 { 1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60 Hz */
45 (SyncPP | Charx8Dot), 60, 2, 0x30 },
46 { 1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72 Hz */
48 { 1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75 Hz */
[all …]
/linux/arch/arm64/boot/dts/axiado/
H A Dax3000.dtsi15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
52 cpu2: cpu@2 {
88 cache-level = <2>;
110 #address-cells = <2>;
111 #size-cells = <2>;
120 #address-cells = <2>;
121 #size-cells = <2>;
135 #gpio-cells = <2>;
[all …]
/linux/drivers/iio/magnetometer/
H A Dst_magn_core.c42 /* Special L addresses for Sensor 2 */
156 { .hz = 1, .value = 0x00 },
157 { .hz = 2, .value = 0x01 },
158 { .hz = 3, .value = 0x02 },
159 { .hz = 8, .value = 0x03 },
160 { .hz = 15, .value = 0x04 },
161 { .hz = 30, .value = 0x05 },
162 { .hz = 75, .value = 0x06 },
163 /* 220 Hz, 0x07 reportedly exist */
188 [2] = {
[all …]
/linux/arch/microblaze/include/asm/
H A Ddelay.h24 * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
25 * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32.
27 * The mul instruction gives us loops = (a * b) / 2^32.
28 * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
29 * because this lets us support a wide range of HZ and
30 * loops_per_jiffy values without either a or b overflowing 2^32.
31 * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
32 * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
33 * (which corresponds to ~3800 bogomips at HZ = 100).
36 #define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd1501s-phantom.dtsi19 #address-cells = <2>;
20 #size-cells = <2>;
38 opp-hz = /bits/ 64 <800000000>;
43 opp-hz = /bits/ 64 <900000000>;
48 opp-hz = /bits/ 64 <1000000000>;
53 opp-hz = /bits/ 64 <1100000000>;
58 opp-hz = /bits/ 64 <1200000000>;
63 opp-hz = /bits/ 64 <1300000000>;
68 opp-hz = /bits/ 64 <1400000000>;
73 opp-hz = /bits/ 64 <1500000000>;
[all …]
H A Drtd1920s-smallville.dtsi19 #address-cells = <2>;
20 #size-cells = <2>;
48 opp-hz = /bits/ 64 <800000000>;
53 opp-hz = /bits/ 64 <900000000>;
58 opp-hz = /bits/ 64 <1000000000>;
63 opp-hz = /bits/ 64 <1100000000>;
68 opp-hz = /bits/ 64 <1200000000>;
73 opp-hz = /bits/ 64 <1300000000>;
78 opp-hz = /bits/ 64 <1400000000>;
83 opp-hz = /bits/ 64 <1500000000>;
[all …]
/linux/arch/arm/include/asm/
H A Ddelay.h11 #include <asm/param.h> /* HZ */
20 * jiffies_per_sec = HZ
23 * Therefore the constant part is HZ / 1000000 which is a small
25 * scale up this constant by 2^31, perform the actual multiplication,
26 * and scale the result back down by 2^31 with a simple shift:
32 * UDELAY_MULT = 2^31 * HZ / 1000000
33 * = (2^31 / 1000000) * HZ
34 * = 2147.483648 * HZ
35 * = 2147 * HZ + 483648 * HZ / 1000000
38 * delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000.
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412.dtsi50 #cooling-cells = <2>; /* min followed by max */
60 #cooling-cells = <2>; /* min followed by max */
70 #cooling-cells = <2>; /* min followed by max */
80 #cooling-cells = <2>; /* min followed by max */
89 opp-hz = /bits/ 64 <200000000>;
94 opp-hz = /bits/ 64 <300000000>;
99 opp-hz = /bits/ 64 <400000000>;
104 opp-hz = /bits/ 64 <500000000>;
109 opp-hz = /bits/ 64 <600000000>;
114 opp-hz = /bits/ 64 <700000000>;
[all …]
H A Dexynos5422-odroid-core.dtsi42 bus_wcore_opp_table: opp-table-2 {
47 opp-hz = /bits/ 64 <88700000>;
51 opp-hz = /bits/ 64 <133000000>;
55 opp-hz = /bits/ 64 <177400000>;
59 opp-hz = /bits/ 64 <266000000>;
63 opp-hz = /bits/ 64 <532000000>;
73 opp-hz = /bits/ 64 <66600000>;
76 opp-hz = /bits/ 64 <74000000>;
79 opp-hz = /bits/ 64 <83250000>;
82 opp-hz = /bits/ 64 <111000000>;
[all …]
H A Dexynos4212.dtsi44 #cooling-cells = <2>; /* min followed by max */
54 #cooling-cells = <2>; /* min followed by max */
63 opp-hz = /bits/ 64 <200000000>;
68 opp-hz = /bits/ 64 <300000000>;
73 opp-hz = /bits/ 64 <400000000>;
78 opp-hz = /bits/ 64 <500000000>;
83 opp-hz = /bits/ 64 <600000000>;
88 opp-hz = /bits/ 64 <700000000>;
93 opp-hz = /bits/ 64 <800000000>;
99 opp-hz = /bits/ 64 <900000000>;
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt602x-common.dtsi5 * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C"
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
97 cpu_e02: cpu@2 {
239 cache-level = <2>;
246 cache-level = <2>;
251 l2_cache_2: l2-cache-2 {
253 cache-level = <2>;
263 /* pstate #1 is a dummy clone of #2 */
[all …]
H A Dt600x-common.dtsi5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
205 cache-level = <2>;
212 cache-level = <2>;
217 l2_cache_2: l2-cache-2 {
219 cache-level = <2>;
229 opp-hz = /bits/ 64 <600000000>;
234 opp-hz = /bits/ 64 <972000000>;
[all …]
/linux/arch/mips/sni/
H A Dtime.c15 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
59 * a20r platform uses 2 counters to divide the input frequency.
60 * Counter 2 output is connected to Counter 0 & 1 input.
76 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
103 * for every 1/HZ seconds. We round off the nearest 1 MHz of master in dosample()
104 * clock (= 1000000 / HZ / 2). in dosample()
106 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/ in dosample()
107 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); in dosample()
140 r4k_ticks[2] = dosample(); in plat_time_init()
141 if (r4k_ticks[2] == r4k_ticks[0] in plat_time_init()
[all …]
/linux/drivers/iio/pressure/
H A Dst_pressure_core.c61 * (10^3 / sensitivity) (2)
70 * Matching OFFSET and SCALE with members of (2) gives :
155 IIO_CHAN_SOFT_TIMESTAMP(2)
187 IIO_CHAN_SOFT_TIMESTAMP(2)
221 IIO_CHAN_SOFT_TIMESTAMP(2)
242 { .hz = 1, .value = 0x01 },
243 { .hz = 7, .value = 0x05 },
244 { .hz = 13, .value = 0x06 },
245 { .hz = 25, .value = 0x07 },
298 .bootime = 2,
[all …]
/linux/drivers/pwm/
H A Dpwm-ab8500.c56 * b0000 | 293 Hz | 292.968750 Hz | 3413333.33 ns in ab8500_pwm_apply()
57 * b0001 | 302 Hz | 302.419355 Hz | 3306666.66 ns in ab8500_pwm_apply()
58 * b0010 | 312 Hz | 312.500000 Hz | 3200000 ns in ab8500_pwm_apply()
59 * b0011 | 323 Hz | 323.275862 Hz | 3093333.33 ns in ab8500_pwm_apply()
60 * b0100 | 334 Hz | 334.821429 Hz | 2986666.66 ns in ab8500_pwm_apply()
61 * b0101 | 347 Hz | 347.222222 Hz | 2880000 ns in ab8500_pwm_apply()
62 * b0110 | 360 Hz | 360.576923 Hz | 2773333.33 ns in ab8500_pwm_apply()
63 * b0111 | 375 Hz | 375.000000 Hz | 2666666.66 ns in ab8500_pwm_apply()
64 * b1000 | 390 Hz | 390.625000 Hz | 2560000 ns in ab8500_pwm_apply()
65 * b1001 | 407 Hz | 407.608696 Hz | 2453333.33 ns in ab8500_pwm_apply()
[all …]
H A Dpwm-mc33xs2410.c8 * - Supports frequencies between 0.5Hz and 2048Hz with following steps:
9 * - 0.5 Hz steps from 0.5 Hz to 32 Hz
10 * - 2 Hz steps from 2 Hz to 128 Hz
11 * - 8 Hz steps from 8 Hz to 512 Hz
12 * - 32 Hz steps from 32 Hz to 2048 Hz
59 #define MC33XS2410_PWM_MAX_PERIOD(step) (2000000000 >> (2 * (step)))
83 return spi_write(spi, tx, len * 2); in mc33xs2410_write_regs()
101 t.len = len * 2; in mc33xs2410_read_regs()
169 case MC33XS2410_PWM_MAX_PERIOD(3) + 1 ... MC33XS2410_PWM_MAX_PERIOD(2): in mc33xs2410_pwm_get_freq()
170 step = 2; in mc33xs2410_pwm_get_freq()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650.dtsi34 #address-cells = <2>;
35 #size-cells = <2>;
56 clock-div = <2>;
65 clock-div = <2>;
70 #address-cells = <2>;
99 #cooling-cells = <2>;
103 cache-level = <2>;
141 #cooling-cells = <2>;
170 #cooling-cells = <2>;
174 cache-level = <2>;
[all …]
/linux/include/sound/sof/
H A Dstream.h21 #define SOF_RATE_8000 (1 << 0) /**< 8000Hz */
22 #define SOF_RATE_11025 (1 << 1) /**< 11025Hz */
23 #define SOF_RATE_12000 (1 << 2) /**< 12000Hz */
24 #define SOF_RATE_16000 (1 << 3) /**< 16000Hz */
25 #define SOF_RATE_22050 (1 << 4) /**< 22050Hz */
26 #define SOF_RATE_24000 (1 << 5) /**< 24000Hz */
27 #define SOF_RATE_32000 (1 << 6) /**< 32000Hz */
28 #define SOF_RATE_44100 (1 << 7) /**< 44100Hz */
29 #define SOF_RATE_48000 (1 << 8) /**< 48000Hz */
30 #define SOF_RATE_64000 (1 << 9) /**< 64000Hz */
[all …]

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