Home
last modified time | relevance | path

Searched full:24 (Results 1 – 25 of 1203) sorted by relevance

12345678910>>...49

/qemu/tests/tcg/alpha/system/
H A Dboot.S21 sll \reg, 24, \reg
197 * These do not follow the C calling convention. Arguments are in $24+$25,
218 stq $3, 24($sp)
230 mov $24, modulus
255 ldq $3, 24($sp)
301 bis $24, $25, $28
307 stq $24, 8($sp)
311 subq $31, $24, $28
312 cmovlt $24, $28, $24
318 ldq $24, 8($sp)
[all …]
/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
48 XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
123 …2:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:6…
125 …24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:…
127 …2:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:6…
129 …2:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:6…
131 …0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:0…
133 …0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:0…
135 …0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:0…
137 …0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:0…
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
23 F2(RRE, R(1,24), R(2,28))
24 F3(RRD, R(1,16), R(2,28), R(3,24))
25 F4(RRF_a, R(1,24), R(2,28), R(3,16), M(4,20))
26 F4(RRF_b, R(1,24), R(2,28), R(3,16), M(4,20))
27 F4(RRF_c, R(1,24), R(2,28), M(3,16), M(4,20))
28 F4(RRF_d, R(1,24), R(2,28), M(3,16), M(4,20))
29 F4(RRF_e, R(1,24), R(2,28), M(3,16), M(4,20))
58 F4(VRI_b, V(1,8), I(2,16,8), I(3,24,8), M(4,32))
60 F5(VRI_d, V(1,8), V(2,12), V(3,16), I(4,24,8), M(5,32))
[all …]
/qemu/crypto/
H A Daes.c41 # define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt…
42 # define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((s…
967 rol32(AES_mc_rot[st->b[swap_b ^ 0x3]], 24)); in aesenc_MC_swap()
976 rol32(AES_mc_rot[st->b[swap_b ^ 0x7]], 24)); in aesenc_MC_swap()
985 rol32(AES_mc_rot[st->b[swap_b ^ 0xB]], 24)); in aesenc_MC_swap()
994 rol32(AES_mc_rot[st->b[swap_b ^ 0xF]], 24)); in aesenc_MC_swap()
1129 rol32(AES_imc_rot[st->b[swap_b ^ 0x3]], 24)); in aesdec_IMC_swap()
1138 rol32(AES_imc_rot[st->b[swap_b ^ 0x7]], 24)); in aesdec_IMC_swap()
1147 rol32(AES_imc_rot[st->b[swap_b ^ 0xB]], 24)); in aesdec_IMC_swap()
1156 rol32(AES_imc_rot[st->b[swap_b ^ 0xF]], 24)); in aesdec_IMC_swap()
[all …]
/qemu/include/hw/misc/
H A Dxlnx-zynqmp-crf.h30 FIELD(APLL_CTRL, POST_SRC, 24, 3)
50 FIELD(DPLL_CTRL, POST_SRC, 24, 3)
70 FIELD(VPLL_CTRL, POST_SRC, 24, 3)
104 FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
108 FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
112 FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
116 FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
121 FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
126 FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
131 FIELD(DDR_CTRL, CLKACT, 24, 1)
[all …]
H A Daspeed_scu.h60 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
133 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
150 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
152 * The default frequency is 792Mhz when CLKIN = 24MHz
163 * 26:24 DRAM configuration setting
194 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24)
195 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
272 * 24 Select DDR4 SDRAM
304 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
341 * 24 Enable H-PLL bypass mode
[all …]
/qemu/tests/qemu-iotests/
H A D314.out13 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
29 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
31 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
33 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
35 24 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
H A D261.out33 Extra data size: 24
48 Extra data size: 24
68 Extra data size: 24
83 Extra data size: 24
95 Extra data size: 24
110 Extra data size: 24
117 Extra data size: 24
138 Extra data size: 24
149 Extra data size: 24
156 Extra data size: 24
[all …]
H A D160.out6 wrote 524288/524288 bytes at offset 24
18 wrote 524288/524288 bytes at offset 24
30 wrote 524288/524288 bytes at offset 24
42 wrote 524288/524288 bytes at offset 24
/qemu/tests/tcg/xtensa/
H A Dtest_cache.S64 cache_fault dpfl, 0x00002345, 24
71 cache_fault dhwb, 0x00002345, 24
75 cache_fault dhwbi, 0x00002345, 24
80 cache_fault dhi, 0x00002345, 24
85 cache_fault dhu, 0x00002345, 24
/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c96 FIELD(INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 24, 6)
179 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1)
212 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1)
245 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1)
285 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS24, 24,
339 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1)
365 FIELD(RX_FIFO_STATUS_REGISTER, FL_1, 24, 7)
386 FIELD(TB0_DLC_REGISTER, EFC, 24, 1)
390 FIELD(TB_DW0_REGISTER, DATA_BYTES0, 24, 8)
395 FIELD(TB_DW1_REGISTER, DATA_BYTES4, 24, 8)
[all …]
/qemu/tests/rocker/
H A Dport10 simp ssh tut sw1 --cmd "sudo ifconfig sw1p1 11.0.0.1/24"
11 simp ssh tut sw1 --cmd "sudo ifconfig sw1p2 12.0.0.1/24"
15 simp ssh tut h1 --cmd "sudo ifconfig sw1p1 11.0.0.2/24"
16 simp ssh tut h2 --cmd "sudo ifconfig sw1p1 12.0.0.2/24"
H A Dbridge32 simp ssh tut sw1 --cmd "sudo ifconfig br0 11.0.0.3/24"
36 simp ssh tut h1 --cmd "sudo ifconfig sw1p1 11.0.0.1/24"
37 simp ssh tut h2 --cmd "sudo ifconfig sw1p1 11.0.0.2/24"
/qemu/pc-bios/s390-ccw/
H A Dbswap.h16 return ((x & 0x000000ffU) << 24) | ((x & 0x0000ff00U) << 8) | in bswap32()
17 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24); in bswap32()
24 ((x & 0x0000000000ff0000ULL) << 24) | in bswap64()
27 ((x & 0x0000ff0000000000ULL) >> 24) | in bswap64()
/qemu/target/mips/
H A Dcpu.h69 #define FCR31_FS 24
73 ((num) ? (1 << ((num) + 24)) : \
77 ~((num) ? (1 << ((num) + 24)) : \
80 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
220 * Register 24 Register 25 Register 26 Register 27
270 #define CP0_REGISTER_24 24
416 /* CP0 Register 24 */
503 #define MSACSR_FS 24
666 #define CP0PF_GDI 24 /* 29..24 */
672 #define CP0PF_GDW 24 /* 29..24 */
[all …]
/qemu/target/arm/
H A Dsyndrome.h88 #define ARM_EL_ISV_SHIFT 24
177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp14_rt_trap()
187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp15_rt_trap()
197 | (cv << 24) | (cond << 20) | (opc1 << 16) in syn_cp14_rrt_trap()
207 | (cv << 24) | (cond << 20) | (opc1 << 16) in syn_cp15_rrt_trap()
217 | (cv << 24) | (cond << 20) | coproc; in syn_fp_access_trap()
225 | (cv << 24) | (cond << 20) | (1 << 5); in syn_simd_access_trap()
267 (cv << 24) | (cond << 20) | rm; in syn_bxjtrap()
321 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; in syn_swstep()
340 (cv << 24) | (cond << 20) | ti; in syn_wfx()
[all …]
/qemu/hw/display/
H A Dpl110_template.h50 FN_8(24) in glue()
58 FN_8(24) in glue()
78 FN_4(0, 24) in glue()
86 FN_4(0, 24) in glue()
106 FN_2(0, 24) in glue()
114 FN_2(0, 24) in glue()
130 FN(24) in glue()
138 FN(24) in glue()
210 LSB = (data >> 24) & 0xff; in glue()
H A Dtcx.c103 if (s->depth == 24) { in tcx_set_dirty()
118 if (s->depth == 24) { in tcx_check_dirty()
179 * detect if line/page/whole screen is in 24 bit mode
192 /* 24-bit direct, BGR order */ in tcx24_draw_line32()
389 val = s->r[s->dac_index] << 24; in tcx_dac_readl()
393 val = s->g[s->dac_index] << 24; in tcx_dac_readl()
397 val = s->b[s->dac_index] << 24; in tcx_dac_readl()
416 s->dac_index = val >> 24; in tcx_dac_writel()
428 s->r[index] = val >> 24; in tcx_dac_writel()
433 s->g[index] = val >> 24; in tcx_dac_writel()
[all …]
/qemu/include/hw/usb/
H A Ddwc2-regs.h99 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
147 #define GINTSTS_PRTINT BIT(24)
206 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
207 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
222 #define GI2CCTL_ACK BIT(24)
244 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
245 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
308 #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
337 #define GLPMCFG_SNDLPM BIT(24)
359 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_snd.h195 VIRTIO_SND_PCM_FMT_S18_3, /* 18 / 24 bits */
196 VIRTIO_SND_PCM_FMT_U18_3, /* 18 / 24 bits */
197 VIRTIO_SND_PCM_FMT_S20_3, /* 20 / 24 bits */
198 VIRTIO_SND_PCM_FMT_U20_3, /* 20 / 24 bits */
199 VIRTIO_SND_PCM_FMT_S24_3, /* 24 / 24 bits */
200 VIRTIO_SND_PCM_FMT_U24_3, /* 24 / 24 bits */
203 VIRTIO_SND_PCM_FMT_S24, /* 24 / 32 bits */
204 VIRTIO_SND_PCM_FMT_U24, /* 24 / 32 bits */
445 uint8_t status[24];
/qemu/target/arm/tcg/
H A Dop_addsub.c.inc42 ADD8(a >> 24, b >> 24, 3);
66 SUB8(a >> 24, b >> 24, 3);
/qemu/include/hw/intc/
H A Dioapic.h23 #define IOAPIC_NUM_PINS 24
26 #define IO_APIC_SECONDARY_IRQBASE 24 /* primary 0 -> 23, secondary 24 -> 47 */
/qemu/target/sparc/
H A Dcpu.c207 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; in cpu_sparc_set_id()
215 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
224 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
233 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
242 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
251 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
260 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
269 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
278 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
287 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
[all …]
/qemu/docs/system/
H A Dcpu-models-mips.rst.inc31 ``24Kc``, ``24KEc``, ``24Kf``
32 MIPS32 Processor (24K, 2003)
/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h42 #define I2C_WATERMARK_LOW PPC_BITMASK(24, 27)
70 #define I2C_INTR_STOP_ERR PPC_BIT(24)
98 #define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31)
124 #define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24)

12345678910>>...49