Lines Matching full:24

60 #define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
133  *  (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
150  *  (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
152  * The default frequency is 792Mhz when CLKIN = 24MHz
163  * 26:24  DRAM configuration setting
194 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x)        ((x) << 24)
195 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK      (0x7 << 24)
272  * 24     Select DDR4 SDRAM
304 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE           (0x1 << 24)
341  *  24     Enable H-PLL bypass mode
351 #define SCU_AST2600_H_PLL_BYPASS_EN                        (0x1 << 24)
363  *  26:24  MAC AHB clock divider selection
386  *  24     Reserved