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/qemu/tests/tcg/alpha/system/
H A Dboot.S213 .frame $sp, 48, $23
258 ret $31, ($23), 1
278 .frame $sp, 16, $23
280 stq $23, 0($sp)
283 bsr $23, __divqu
285 ldq $23, 0($sp)
288 ret $31, ($23), 1
306 stq $23, 0($sp)
316 bsr $23, __divqu
322 subq $31, $27, $23
[all …]
/qemu/include/hw/misc/
H A Daspeed_scu.h105 * 25:23 APB PCLK divider selection
119 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
164 * 23 Enable 25 MHz reference clock input
169 * 23,18 Clock source selection
202 /* bit 23, 18 [1,0] */
203 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
205 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
207 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
208 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
273 * 23 Select 25 MHz reference clock input mode
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_extr_rs_w.c20 dsp = (dsp >> 23) & 0x01; in main()
43 dsp = (dsp >> 23) & 0x01; in main()
66 dsp = (dsp >> 23) & 0x01; in main()
89 dsp = (dsp >> 23) & 0x01; in main()
112 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extr_s_h.c20 dsp = (dsp >> 23) & 0x01; in main()
35 dsp = (dsp >> 23) & 0x01; in main()
58 dsp = (dsp >> 23) & 0x01; in main()
81 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extr_r_w.c20 dsp = (dsp >> 23) & 0x01; in main()
43 dsp = (dsp >> 23) & 0x01; in main()
66 dsp = (dsp >> 23) & 0x01; in main()
89 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extr_w.c20 dsp = (dsp >> 23) & 0x01; in main()
43 dsp = (dsp >> 23) & 0x01; in main()
66 dsp = (dsp >> 23) & 0x01; in main()
89 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extrv_s_h.c24 dsp = (dsp >> 23) & 0x01; in main()
41 dsp = (dsp >> 23) & 0x01; in main()
66 dsp = (dsp >> 23) & 0x01; in main()
83 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extrv_rs_w.c22 dsp = (dsp >> 23) & 0x01; in main()
47 dsp = (dsp >> 23) & 0x01; in main()
72 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extrv_r_w.c24 dsp = (dsp >> 23) & 0x01; in main()
49 dsp = (dsp >> 23) & 0x01; in main()
74 dsp = (dsp >> 23) & 0x01; in main()
H A Dtest_dsp_r1_extrv_w.c24 dsp = (dsp >> 23) & 0x01; in main()
49 dsp = (dsp >> 23) & 0x01; in main()
74 dsp = (dsp >> 23) & 0x01; in main()
/qemu/tests/unit/
H A Dcheck-block-qdict.c55 * 23, in qdict_flatten_test()
76 * "e.1.0": 23, in qdict_flatten_test()
91 qlist_append_int(e_1, 23); in qdict_flatten_test()
113 g_assert(qdict_get_int(root, "e.1.0") == 23); in qdict_flatten_test()
175 * "0.b": 23, in qdict_array_split_test()
184 * "b": 23 in qdict_array_split_test()
208 qdict_put_int(test_dict, "0.b", 23); in qdict_array_split_test()
225 g_assert(qdict_get_int(dict1, "b") == 23); in qdict_array_split_test()
253 * "1": 23, in qdict_array_split_test()
266 * "1": 23, in qdict_array_split_test()
[all …]
/qemu/target/hexagon/imported/
H A Diclass.def27 DEF_PP_ICLASS32(S_2op,23,SUNIT|MUNIT) /* 8 */
31 DEF_PP_ICLASS32(S_3op,23,SUNIT|MUNIT) /* 12 */
32 DEF_PP_ICLASS32(ALU64,23,SUNIT|MUNIT) /* 13 */
33 DEF_PP_ICLASS32(M,23,SUNIT|MUNIT) /* 14 */
/qemu/target/mips/
H A Dcpu.h56 #define FCR0_HAS2008 23
74 (1 << 23)); \
78 (1 << 23)); \
81 (((env).fcr31 >> 23) & 0x1))
207 * Register 20 Register 21 Register 22 Register 23
269 #define CP0_REGISTER_23 23
408 /* CP0 Register 23 */
482 #define CP0TCSt_RNST 23
667 #define CP0PF_UDI 18 /* 23..18 */
673 #define CP0PF_UDW 18 /* 23..18 */
[all …]
/qemu/tests/qemu-iotests/
H A D06683 $QEMU_IO -c "write -P 23 $(((1024 + 32) * 1024)) 192k" "$TEST_IMG" \
91 -c "read -P 23 $(((1024 + 32) * 1024)) 192k" \
125 $QEMU_IO -c 'write -P 23 0 64k' "$TEST_IMG" | _filter_qemu_io
131 $QEMU_IO -c 'read -P 23 0 64k' "$TEST_IMG" | _filter_qemu_io
/qemu/include/hw/usb/
H A Ddwc2-regs.h73 #define GAHBCFG_AHB_SINGLE BIT(23)
100 #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
148 #define GINTSTS_RESETDET BIT(23)
223 #define GI2CCTL_I2CEN BIT(23)
309 #define GHWCFG4_B_VALID_FILT_EN BIT(23)
361 #define GPWRDN_ADP_INT BIT(23)
398 #define ADPCTL_ADP_TMOUT_INT BIT(23)
443 #define DCFG_DESCDMA_EN BIT(23)
695 #define HCFG_DESCDMA BIT(23)
852 #define HOST_DMA_ALT_QTD BIT(23)
[all …]
/qemu/linux-user/ppc/
H A Dvdso.S114 .cfi_offset 23, 23 * sizeof_reg
150 .cfi_offset 55, offsetof_mcontext_fregs + 23 * sizeof_freg
209 save_vreg 23
/qemu/linux-user/hppa/
H A Dvdso.S79 .cfi_offset 23, offsetof_sigcontext_gr + 23 * 4
128 .cfi_offset 70, offsetof_sigcontext_fr + 23 * 8
129 .cfi_offset 71, offsetof_sigcontext_fr + 23 * 8 + 4
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc55 GEN_VXFORM_300(bcdsr, 0, 23),
79 GEN_VXFORM_207(vpksdss, 7, 23),
155 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
162 GEN_VXFORM_300(vbpermd, 6, 23),
169 GEN_VXFORM_207(vsbox, 4, 23),
/qemu/tests/tcg/hexagon/
H A Dtest_bitcnt.S4 * The number 0x000001aa has 23 leading zeroes
20 p0 = cmp.eq(r2, #23); if (p0.new) jump:t test2
/qemu/linux-user/loongarch64/
H A Dvdso.S80 .cfi_offset 23, B_GR + 23 * 8
114 .cfi_offset 55, B_FR + 23 * 8
/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h69 #define I2C_INTR_CMD_COMP PPC_BIT(23)
97 #define I2C_STAT_INTERFACE_BUSY PPC_BIT(23)
123 #define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23)
/qemu/docs/interop/
H A Dparallels.rst50 20 - 23: heads
155 8 - 23: m_CheckSum
188 20 - 23: unused32
208 8 - 23: id
/qemu/target/arm/tcg/
H A Dvfp_helper.c730 int f32_exp = extract32(f32_val, 23, 8); in do_recpe_f32()
731 uint32_t f32_frac = extract32(f32_val, 0, 23); in do_recpe_f32()
765 ((uint64_t) f32_frac) << (52 - 23), rpres); in do_recpe_f32()
769 f32_val = deposit32(f32_val, 23, 8, f32_exp); in do_recpe_f32()
770 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); in do_recpe_f32()
981 int f32_exp = extract32(val, 23, 8); in do_rsqrte_f32()
982 uint32_t f32_frac = extract32(val, 0, 23); in do_rsqrte_f32()
1020 val = deposit32(val, 23, 8, f32_exp); in do_rsqrte_f32()
1086 input = extract32(a, 23, 9); in HELPER()
1100 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); in HELPER()
[all …]
/qemu/hw/ppc/
H A Dspapr_vhyp_mmu.c453 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); in rehash_hpte()
462 /* We only have 28 - 23 bits of offset in avpn */ in rehash_hpte()
463 offset = (avpn & 0x1f) << 23; in rehash_hpte()
466 if (base_pg_shift < 23) { in rehash_hpte()
474 /* We only have 40 - 23 bits of seg_off in avpn */ in rehash_hpte()
475 offset = (avpn & 0x1ffff) << 23; in rehash_hpte()
477 if (base_pg_shift < 23) { in rehash_hpte()
/qemu/hw/intc/
H A Dxlnx-pmu-iomod-intc.c86 FIELD(GPO3, PL_GPO_23, 23, 1)
119 FIELD(GPI0, RFT_MISMATCH_STATE, 23, 1)
144 FIELD(GPI1, ACPU_3_DBG_PWRUP, 23, 1)
169 FIELD(GPI2, DBG_ACPU3_RST_REQ, 23, 1)
194 FIELD(GPI3, PL_GPI_23, 23, 1)
226 FIELD(IRQ_STATUS, FW_REQ, 23, 1)
250 FIELD(IRQ_PENDING, FW_REQ, 23, 1)
274 FIELD(IRQ_ENABLE, FW_REQ, 23, 1)
298 FIELD(IRQ_ACK, FW_REQ, 23, 1)

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