Lines Matching full:23

105  *  25:23  APB PCLK divider selection
119 #define SCU_CLK_GET_PCLK_DIV(x)                    (((x) >> 23) & 0x7)
164  * 23     Enable 25 MHz reference clock input
169  * 23,18  Clock source selection
202 /* bit 23, 18 [1,0] */
203 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x)     (((((x) & 0x3) >> 1) << 23) \
205 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x)     (((((x) >> 23) & 0x1) << 1) \
207 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK       ((0x1 << 23) | (0x1 << 18))
208 #define SCU_HW_STRAP_CLK_25M_IN                    (0x1 << 23)
273  * 23     Select 25 MHz reference clock input mode
305 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE       (0x1 << 23)
342  *  23     Turn off H-PLL
352 #define SCU_AST2600_H_PLL_OFF                              (0x1 << 23)
387  *  23:21  RMIICLK_DIV