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/qemu/target/mips/tcg/
H A Dtranslate.h66 #define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
76 FMT_L = 21, /* 64-bit fixed */
82 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
83 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
84 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
85 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
86 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
87 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
88 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
89 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
[all …]
H A Dtranslate.c184 OPC_ROTR = OPC_SRL | (1 << 21),
196 OPC_DROTR = OPC_DSRL | (1 << 21),
200 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
893 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
896 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
897 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
898 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
899 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
900 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
901 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
[all …]
/qemu/target/ppc/
H A Dinternal.h111 EXTRACT_HELPER(rD, 21, 5);
113 EXTRACT_HELPER(rS, 21, 5);
124 EXTRACT_HELPER(crbD, 21, 5);
159 EXTRACT_HELPER(TO, 21, 5);
181 EXTRACT_HELPER(WC, 21, 2);
196 EXTRACT_HELPER(BO, 21, 5);
210 EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
211 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
212 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
/qemu/tests/tcg/aarch64/system/
H A Dboot.S267 /* Stage 2 entries: indexed by IA[29:21] */
268 ldr x5, =(((1 << 9) - 1) << 21)
272 bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
273 and x4, x1, x5 /* IA[29:21] */
274 add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
282 bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
283 and x4, x1, x5 /* IA[29:21] */
284 add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
292 bic x1, x1, #(1 << 21) - 1
294 add x2, x0, x4, lsr #(21 - 3)
/qemu/hw/mips/
H A Dbootloader.c39 BL_REG_S5 = 21,
91 insn = deposit32(insn, 21, 5, rs); in bl_gen_r_type()
110 insn = deposit32(insn, 21, 5, rs); in bl_gen_i_type()
136 insn = deposit32(insn, 21, 5, BL_REG_RA); in bl_gen_jalr()
151 insn = deposit32(insn, 21, 5, rt); in bl_gen_lui_nm()
171 insn = deposit32(insn, 21, 5, rt); in bl_gen_ori_nm()
189 insn = deposit32(insn, 21, 5, rt); in bl_gen_sw_nm()
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r2_mul_s_ph.c20 dsp = (dsp >> 21) & 0x01; in main()
35 dsp = (dsp >> 21) & 0x01; in main()
57 dsp = (dsp >> 21) & 0x01; in main()
H A Dtest_dsp_r2_mulq_s_ph.c20 dsp = (dsp >> 21) & 0x01; in main()
35 dsp = (dsp >> 21) & 0x01; in main()
H A Dtest_dsp_r1_mulq_rs_ph.c21 dsp = (dsp >> 21) & 0x01; in main()
37 dsp = (dsp >> 21) & 0x01; in main()
H A Dtest_dsp_r1_muleq_s_w_phr.c20 dsp = (dsp >> 21) & 0x01; in main()
35 dsp = (dsp >> 21) & 0x01; in main()
H A Dtest_dsp_r1_muleq_s_w_phl.c20 dsp = (dsp >> 21) & 0x01; in main()
35 dsp = (dsp >> 21) & 0x01; in main()
H A Dtest_dsp_r2_mul_ph.c20 dsp = (dsp >> 21) & 0x01; in main()
42 dsp = (dsp >> 21) & 0x01; in main()
/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h33 #define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21)
67 #define I2C_INTR_NACK_RCVD_ERR PPC_BIT(21)
95 #define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21)
121 #define I2C_EXTD_STAT_M_SDA PPC_BIT(21)
/qemu/target/i386/
H A Dmonitor.c83 print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); in tlb_info_32()
117 print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, in tlb_info_pae32()
125 print_pte(mon, env, (l1 << 30) + (l2 << 21) in tlb_info_pae32()
179 (l3 << 21), pde, 0x3ffffffe00000ULL); in tlb_info_la48()
191 (l2 << 30) + (l3 << 21) + (l4 << 12), in tlb_info_la48()
335 end = (l1 << 30) + (l2 << 21); in mem_info_pae32()
346 end = (l1 << 30) + (l2 << 21) + (l3 << 12); in mem_info_pae32()
403 end = (l1 << 39) + (l2 << 30) + (l3 << 21); in mem_info_la48()
419 (l3 << 21) + (l4 << 12); in mem_info_la48()
506 end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21); in mem_info_la57()
[all …]
/qemu/target/mips/
H A Dcpu.h58 #define FCR0_L 21
207 * Register 20 Register 21 Register 22 Register 23
267 #define CP0_REGISTER_21 21
406 /* CP0 Register 21 */
483 #define CP0TCSt_TDS 21
491 #define CP0TCBd_CurTC 21
561 #define CP0VPECo_YSI 21
568 #define CP0VPEC0_XTC 21
775 #define CP0St_TS 21
861 #define CP0C1_IL 19 /* 21..19 */
[all …]
/qemu/linux-user/ppc/
H A Dvdso.S112 .cfi_offset 21, 21 * sizeof_reg
148 .cfi_offset 53, offsetof_mcontext_fregs + 21 * sizeof_freg
207 save_vreg 21
/qemu/linux-user/hppa/
H A Dvdso.S77 .cfi_offset 21, offsetof_sigcontext_gr + 21 * 4
124 .cfi_offset 66, offsetof_sigcontext_fr + 21 * 8
125 .cfi_offset 67, offsetof_sigcontext_fr + 21 * 8 + 4
/qemu/linux-user/loongarch64/
H A Dvdso.S78 .cfi_offset 21, B_GR + 21 * 8
112 .cfi_offset 53, B_FR + 21 * 8
/qemu/include/hw/misc/
H A Dxlnx-versal-cframe-reg.h80 FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
105 FIELD(CFRM_IMR0, READ_BROADCAST_ERROR, 21, 1)
130 FIELD(CFRM_IER0, READ_BROADCAST_ERROR, 21, 1)
155 FIELD(CFRM_IDR0, READ_BROADCAST_ERROR, 21, 1)
180 FIELD(CFRM_ITR0, READ_BROADCAST_ERROR, 21, 1)
/qemu/include/hw/usb/
H A Ddwc2-regs.h75 #define GAHBCFG_REM_MEM_SUPP BIT(21)
102 #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
150 #define GINTSTS_INCOMPL_IP BIT(21)
151 #define GINTSTS_INCOMPL_SOOUT BIT(21)
311 #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
338 #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
339 #define GLPMCFG_RETRY_CNT_SHIFT 21
340 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
363 #define GPWRDN_IDSTS BIT(21)
400 #define ADPCTL_ADP_PRB_INT BIT(21)
[all …]
/qemu/linux-user/riscv/
H A Dvdso.S136 .cfi_offset 21, B_GR + 21 * sizeof_reg
169 .cfi_offset 53, B_FR + 21 * sizeof_freg
/qemu/tests/tcg/tricore/asm/
H A Dtest_dextr.S27 TEST_D_DDI(dextr, 21, 0xf0123456, 0xabcdef01, 0x23456789, 20)
28 TEST_D_DDI(dextr, 22, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
63 TEST_D_DDD(dextr, 55, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc65 GEN_VXFORM_300(bcdutrunc, 0, 21),
76 GEN_VXFORM_207(vpksdus, 7, 21),
163 GEN_VXFORM_207(vbpermq, 6, 21),
172 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
/qemu/tests/tcg/arm/
H A Dfcvt.ref46 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
47 21 HALF: 0x7bff (0 => OK)
109 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
110 21 DOUBLE: 6.55040000000000000000e+04 / 0x0040effc0000000000 (0 => OK)
172 21 DOUBLE: 1.37899728486072282843e-308 / 0x000009ea82a2287680 (0 => OK)
173 21 HALF: 0000 (0x10 => INEXACT )
255 21 DOUBLE: 1.37899728486072282843e-308 / 0x000009ea82a2287680 (0 => OK)
256 21 SINGLE: 0.00000000000000000000e+00 / 0000000000 (0x18 => UNDERFLOW INEXACT )
409 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
410 21 HALF: 0x7bff (0 => OK)
[all …]
/qemu/tests/tcg/aarch64/
H A Dfcvt.ref46 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
47 21 HALF: 0x7bff (0 => OK)
109 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
110 21 DOUBLE: 6.55040000000000000000e+04 / 0x0040effc0000000000 (0 => OK)
172 21 DOUBLE: 1.37899728486072282843e-308 / 0x000009ea82a2287680 (0 => OK)
173 21 HALF: 0000 (0x18 => UNDERFLOW INEXACT )
255 21 DOUBLE: 1.37899728486072282843e-308 / 0x000009ea82a2287680 (0 => OK)
256 21 SINGLE: 0.00000000000000000000e+00 / 0000000000 (0x18 => UNDERFLOW INEXACT )
409 21 SINGLE: 6.55040000000000000000e+04 / 0x477fe000 (0 => OK)
410 21 HALF: 0x7bff (0 => OK)
[all …]
/qemu/target/hexagon/
H A Darch.c71 {21, 26, 30, 35},
75 {17, 21, 25, 28},
78 {14, 18, 21, 24},
81 {12, 15, 18, 21},
103 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
114 16, 16, 18, 18, 19, 19, 21, 21, 22, 22,

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