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/linux-5.10/crypto/
Dsha3_generic.c20 * over 1 KB of stack if we inline the round calculation into the loop
47 static SHA3_INLINE void keccakf_round(u64 st[25]) in keccakf_round()
52 bc[0] = st[0] ^ st[5] ^ st[10] ^ st[15] ^ st[20]; in keccakf_round()
53 bc[1] = st[1] ^ st[6] ^ st[11] ^ st[16] ^ st[21]; in keccakf_round()
54 bc[2] = st[2] ^ st[7] ^ st[12] ^ st[17] ^ st[22]; in keccakf_round()
55 bc[3] = st[3] ^ st[8] ^ st[13] ^ st[18] ^ st[23]; in keccakf_round()
56 bc[4] = st[4] ^ st[9] ^ st[14] ^ st[19] ^ st[24]; in keccakf_round()
58 t[0] = bc[4] ^ rol64(bc[1], 1); in keccakf_round()
59 t[1] = bc[0] ^ rol64(bc[2], 1); in keccakf_round()
60 t[2] = bc[1] ^ rol64(bc[3], 1); in keccakf_round()
[all …]
/linux-5.10/Documentation/devicetree/bindings/iio/accel/
Dlis302.txt8 - compatible: should be set to "st,lis3lv02d-spi"
15 - compatible: should be set to "st,lis3lv02d"
23 - st,click-single-{x,y,z}: if present, tells the device to issue an
26 - st,click-double-{x,y,z}: if present, tells the device to issue an
29 - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
30 - st,click-click-time-limit: click time limit, from 0 to 127.5msec
32 - st,click-latency: click latency, from 0 to 255 msec with
33 step of 1 msec.
34 - st,click-window: click window, from 0 to 255 msec with
35 step of 1 msec.
[all …]
/linux-5.10/drivers/staging/iio/frequency/
Dad9832.c72 #define RES_MASK(bits) ((1 << (bits)) - 1)
124 (u64)((u64)1L << AD9832_FREQ_BITS); in ad9832_calc_freqreg()
129 static int ad9832_write_frequency(struct ad9832_state *st, in ad9832_write_frequency() argument
134 if (fout > (clk_get_rate(st->mclk) / 2)) in ad9832_write_frequency()
137 regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout); in ad9832_write_frequency()
139 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
142 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
143 ((addr - 1) << ADD_SHIFT) | in ad9832_write_frequency()
145 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
148 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
[all …]
Dad9834.c49 #define AD9834_MODE BIT(1)
54 #define RES_MASK(bits) (BIT(bits) - 1)
110 static int ad9834_write_frequency(struct ad9834_state *st, in ad9834_write_frequency() argument
116 clk_freq = clk_get_rate(st->mclk); in ad9834_write_frequency()
123 st->freq_data[0] = cpu_to_be16(addr | (regval & in ad9834_write_frequency()
125 st->freq_data[1] = cpu_to_be16(addr | ((regval >> in ad9834_write_frequency()
129 return spi_sync(st->spi, &st->freq_msg); in ad9834_write_frequency()
132 static int ad9834_write_phase(struct ad9834_state *st, in ad9834_write_phase() argument
137 st->data = cpu_to_be16(addr | phase); in ad9834_write_phase()
139 return spi_sync(st->spi, &st->msg); in ad9834_write_phase()
[all …]
/linux-5.10/drivers/iio/adc/
Dat91_adc.c36 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37 #define AT91_ADC_START (1 << 1) /* Start Conversion */
42 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
46 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
47 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
48 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
[all …]
Dad7298.c33 #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
60 .indexed = 1, \
77 .indexed = 1,
83 .scan_index = -1,
91 AD7298_V_CHAN(1),
107 struct ad7298_state *st = iio_priv(indio_dev); in ad7298_update_scan_mode() local
115 command = AD7298_WRITE | st->ext_ref; in ad7298_update_scan_mode()
117 for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1) in ad7298_update_scan_mode()
121 st->tx_buf[0] = cpu_to_be16(command); in ad7298_update_scan_mode()
124 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7298_update_scan_mode()
[all …]
Dad7887.c30 #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
31 #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
33 #define AD7887_PM_MODE2 1 /* full on */
84 struct ad7887_state *st = iio_priv(indio_dev); in ad7887_ring_preenable() local
88 case (1 << 0): in ad7887_ring_preenable()
89 st->ring_msg = &st->msg[AD7887_CH0]; in ad7887_ring_preenable()
91 case (1 << 1): in ad7887_ring_preenable()
92 st->ring_msg = &st->msg[AD7887_CH1]; in ad7887_ring_preenable()
94 spi_sync(st->spi, st->ring_msg); in ad7887_ring_preenable()
96 case ((1 << 1) | (1 << 0)): in ad7887_ring_preenable()
[all …]
Dad7266.c51 static int ad7266_wakeup(struct ad7266_state *st) in ad7266_wakeup() argument
54 return spi_read(st->spi, &st->data.sample[0], 2); in ad7266_wakeup()
57 static int ad7266_powerdown(struct ad7266_state *st) in ad7266_powerdown() argument
60 return spi_read(st->spi, &st->data.sample[0], 1); in ad7266_powerdown()
65 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_preenable() local
66 return ad7266_wakeup(st); in ad7266_preenable()
71 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_postdisable() local
72 return ad7266_powerdown(st); in ad7266_postdisable()
84 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_trigger_handler() local
87 ret = spi_read(st->spi, st->data.sample, 4); in ad7266_trigger_handler()
[all …]
Dad7476.c72 static void ad7091_convst(struct ad7476_state *st) in ad7091_convst() argument
74 if (!st->convst_gpio) in ad7091_convst()
77 gpiod_set_value(st->convst_gpio, 0); in ad7091_convst()
78 udelay(1); /* CONVST pulse width: 10 ns min */ in ad7091_convst()
79 gpiod_set_value(st->convst_gpio, 1); in ad7091_convst()
80 udelay(1); /* Conversion time: 650 ns max */ in ad7091_convst()
87 struct ad7476_state *st = iio_priv(indio_dev); in ad7476_trigger_handler() local
90 ad7091_convst(st); in ad7476_trigger_handler()
92 b_sent = spi_sync(st->spi, &st->msg); in ad7476_trigger_handler()
96 iio_push_to_buffers_with_timestamp(indio_dev, st->data, in ad7476_trigger_handler()
[all …]
Dad7606.c44 1, 2, 4, 8, 16, 32, 64,
48 1, 2, 4, 8, 16, 32, 64, 128,
51 static int ad7606_reset(struct ad7606_state *st) in ad7606_reset() argument
53 if (st->gpio_reset) { in ad7606_reset()
54 gpiod_set_value(st->gpio_reset, 1); in ad7606_reset()
56 gpiod_set_value(st->gpio_reset, 0); in ad7606_reset()
68 struct ad7606_state *st = iio_priv(indio_dev); in ad7606_reg_access() local
71 mutex_lock(&st->lock); in ad7606_reg_access()
73 ret = st->bops->reg_read(st, reg); in ad7606_reg_access()
79 ret = st->bops->reg_write(st, reg, writeval); in ad7606_reg_access()
[all …]
Dti-ads7950.c54 (((val) >> (dec)) & ((1 << (bits)) - 1))
60 #define TI_ADS7950_MAN_CMD_SETTINGS(st) \ argument
61 (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
63 #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \ argument
64 (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
139 .indexed = 1, \
158 TI_ADS7950_V_CHAN(1, bits), \
167 TI_ADS7950_V_CHAN(1, bits), \
180 TI_ADS7950_V_CHAN(1, bits), \
197 TI_ADS7950_V_CHAN(1, bits), \
[all …]
Dad7192.c32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
147 #define AD7192_NO_SYNC_FILTER 1
204 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
206 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
[all …]
Dad7124.c108 1, 2, 4, 8, 16, 32, 64, 128
112 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
162 .indexed = 1,
163 .differential = 1,
211 static int ad7124_spi_write_mask(struct ad7124_state *st, in ad7124_spi_write_mask() argument
220 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); in ad7124_spi_write_mask()
227 return ad_sd_write_reg(&st->sd, addr, bytes, readval); in ad7124_spi_write_mask()
233 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); in ad7124_set_mode() local
235 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; in ad7124_set_mode()
236 st->adc_control |= AD7124_ADC_CTRL_MODE(mode); in ad7124_set_mode()
[all …]
/linux-5.10/drivers/gpu/drm/etnaviv/
Detnaviv_cmd_parser.c26 #define ST(start, num) { (start) >> 2, (num) } macro
28 ST(0x1200, 1),
29 ST(0x1228, 1),
30 ST(0x1238, 1),
31 ST(0x1284, 1),
32 ST(0x128c, 1),
33 ST(0x1304, 1),
34 ST(0x1310, 1),
35 ST(0x1318, 1),
36 ST(0x12800, 4),
[all …]
/linux-5.10/drivers/iio/dac/
Dad5592r-base.c26 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_get() local
30 mutex_lock(&st->gpio_lock); in ad5592r_gpio_get()
32 if (st->gpio_out & BIT(offset)) in ad5592r_gpio_get()
33 val = st->gpio_val; in ad5592r_gpio_get()
35 ret = st->ops->gpio_read(st, &val); in ad5592r_gpio_get()
37 mutex_unlock(&st->gpio_lock); in ad5592r_gpio_get()
47 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_set() local
49 mutex_lock(&st->gpio_lock); in ad5592r_gpio_set()
52 st->gpio_val |= BIT(offset); in ad5592r_gpio_set()
54 st->gpio_val &= ~BIT(offset); in ad5592r_gpio_set()
[all …]
Dad5791.c32 #define AD5791_ADDR_DAC0 1
38 #define AD5791_CTRL_RBUF BIT(1)
46 #define AD5791_LINCOMP_10_12 1
56 #define AD5791_SWCTRL_CLR BIT(1)
60 #define AD5791_DAC_PWRDN_3STATE 1
108 static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val) in ad5791_spi_write() argument
110 st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE | in ad5791_spi_write()
114 return spi_write(st->spi, &st->data[0].d8[1], 3); in ad5791_spi_write()
117 static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val) in ad5791_spi_read() argument
122 .tx_buf = &st->data[0].d8[1], in ad5791_spi_read()
[all …]
/linux-5.10/drivers/staging/iio/resolver/
Dad2s1210.c103 [MOD_VEL] = { 0, 1 },
104 [MOD_CONFIG] = { 1, 0 },
108 struct ad2s1210_state *st) in ad2s1210_set_mode() argument
110 gpiod_set_value(st->gpios[AD2S1210_A0], ad2s1210_mode_vals[mode][0]); in ad2s1210_set_mode()
111 gpiod_set_value(st->gpios[AD2S1210_A1], ad2s1210_mode_vals[mode][1]); in ad2s1210_set_mode()
112 st->mode = mode; in ad2s1210_set_mode()
115 /* write 1 bytes (address or data) to the chip */
116 static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data) in ad2s1210_config_write() argument
120 ad2s1210_set_mode(MOD_CONFIG, st); in ad2s1210_config_write()
121 st->tx[0] = data; in ad2s1210_config_write()
[all …]
/linux-5.10/drivers/macintosh/
Dwindfarm_pid.c25 void wf_pid_init(struct wf_pid_state *st, struct wf_pid_param *param) in wf_pid_init() argument
27 memset(st, 0, sizeof(struct wf_pid_state)); in wf_pid_init()
28 st->param = *param; in wf_pid_init()
29 st->first = 1; in wf_pid_init()
33 s32 wf_pid_run(struct wf_pid_state *st, s32 new_sample) in wf_pid_run() argument
37 int i, hlen = st->param.history_len; in wf_pid_run()
40 error = new_sample - st->param.itarget; in wf_pid_run()
43 if (st->first) { in wf_pid_run()
45 st->samples[i] = new_sample; in wf_pid_run()
46 st->errors[i] = error; in wf_pid_run()
[all …]
/linux-5.10/drivers/iio/accel/
Dsca3000.c34 #define SCA3000_EEPROM_CS_ERROR BIT(1)
63 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
77 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
109 #define SCA3000_MD_CTRL_OR_X BIT(1)
182 * @option_mode_1_freq: option mode 1 sampling frequency
277 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) in sca3000_write_reg() argument
279 st->tx[0] = SCA3000_WRITE_REG(address); in sca3000_write_reg()
280 st->tx[1] = val; in sca3000_write_reg()
281 return spi_write(st->us, st->tx, 2); in sca3000_write_reg()
284 static int sca3000_read_data_short(struct sca3000_state *st, in sca3000_read_data_short() argument
[all …]
/linux-5.10/drivers/staging/iio/impedance-analyzer/
Dad5933.c26 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 1 byte */
27 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 1 byte */
32 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
46 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
47 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
48 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
49 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
50 #define AD5933_CTRL_RANGE(x) ((x) << 1)
62 #define AD5933_STAT_DATA_VALID (0x1 << 1)
75 #define AD5933_OUT_RANGE 1
[all …]
/linux-5.10/drivers/iio/common/hid-sensors/
Dhid-sensor-attributes.c29 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
35 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
41 HID_USAGE_SENSOR_UNITS_RADIANS_PER_SECOND, 1, 0},
46 {HID_USAGE_SENSOR_COMPASS_3D, HID_USAGE_SENSOR_UNITS_GAUSS, 1, 0},
52 HID_USAGE_SENSOR_UNITS_RADIANS, 1, 0},
54 {HID_USAGE_SENSOR_ALS, 0, 1, 0},
55 {HID_USAGE_SENSOR_ALS, HID_USAGE_SENSOR_UNITS_LUX, 1, 0},
64 {HID_USAGE_SENSOR_DEVICE_ORIENTATION, 0, 1, 0},
66 {HID_USAGE_SENSOR_RELATIVE_ORIENTATION, 0, 1, 0},
68 {HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION, 0, 1, 0},
[all …]
/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-dfsdm-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@st.com>
11 - Olivier Moysan <olivier.moysan@st.com>
28 - st,stm32h7-dfsdm
29 - st,stm32mp1-dfsdm
32 maxItems: 1
40 minItems: 1
47 minItems: 1
51 const: 1
82 - st,stm32-dfsdm-adc
[all …]
/linux-5.10/drivers/staging/iio/adc/
Dad7280a.c69 #define AD7280A_CTRL_HB_CONV_AVG_2 BIT(1)
71 #define AD7280A_CTRL_HB_CONV_AVG_8 (BIT(2) | BIT(1))
72 #define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1)
84 #define AD7280A_CTRL_LB_INC_DEV_ADDR BIT(1)
92 #define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
97 AD7280A_CELL_VOLTAGE_1 + 1)
126 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F
160 static int ad7280_check_crc(struct ad7280_state *st, unsigned int val) in ad7280_check_crc() argument
162 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10); in ad7280_check_crc()
178 static void ad7280_delay(struct ad7280_state *st) in ad7280_delay() argument
[all …]
/linux-5.10/drivers/iio/imu/inv_mpu6050/
Dinv_mpu_magn.c47 static bool inv_magn_supported(const struct inv_mpu6050_state *st) in inv_magn_supported() argument
49 switch (st->chip_type) { in inv_magn_supported()
60 static int inv_magn_init(struct inv_mpu6050_state *st) in inv_magn_init() argument
68 ret = inv_mpu_aux_read(st, INV_MPU_MAGN_I2C_ADDR, INV_MPU_MAGN_REG_WIA, in inv_magn_init()
76 switch (st->chip_type) { in inv_magn_init()
79 ret = inv_mpu_aux_write(st, INV_MPU_MAGN_I2C_ADDR, in inv_magn_init()
90 ret = inv_mpu_aux_write(st, INV_MPU_MAGN_I2C_ADDR, in inv_magn_init()
96 ret = inv_mpu_aux_read(st, INV_MPU_MAGN_I2C_ADDR, INV_MPU_MAGN_REG_ASAX, in inv_magn_init()
102 ret = inv_mpu_aux_write(st, INV_MPU_MAGN_I2C_ADDR, in inv_magn_init()
110 * 1 uT = 0.01 G and value is in micron (1e6) in inv_magn_init()
[all …]
/linux-5.10/drivers/iio/frequency/
Dadf4350.c73 static int adf4350_sync_config(struct adf4350_state *st) in adf4350_sync_config() argument
78 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
83 doublebuf = 1; in adf4350_sync_config()
87 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
88 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
91 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
92 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
93 i, (u32)st->regs[i] | i); in adf4350_sync_config()
103 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_reg_access() local
109 mutex_lock(&st->lock); in adf4350_reg_access()
[all …]

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