Lines Matching +full:1 +full:st
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
147 #define AD7192_NO_SYNC_FILTER 1
204 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
206 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
214 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_get_syscalib_mode() local
216 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
224 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_syscalib() local
232 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
271 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_channel() local
273 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
274 st->conf |= AD7192_CONF_CHAN(channel); in ad7192_set_channel()
276 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
282 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_mode() local
284 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
285 st->mode |= AD7192_MODE_SEL(mode); in ad7192_set_mode()
287 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
309 static int ad7192_calibrate_all(struct ad7192_state *st) in ad7192_calibrate_all() argument
311 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
321 static int ad7192_of_clock_select(struct ad7192_state *st) in ad7192_of_clock_select() argument
323 struct device_node *np = st->sd.spi->dev.of_node; in ad7192_of_clock_select()
329 if (PTR_ERR(st->mclk) == -ENOENT) { in ad7192_of_clock_select()
342 static int ad7192_setup(struct ad7192_state *st, struct device_node *np) in ad7192_setup() argument
344 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); in ad7192_setup()
351 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
357 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
363 if (id != st->chip_info->chip_id) in ad7192_setup()
364 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", in ad7192_setup()
367 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | in ad7192_setup()
368 AD7192_MODE_CLKSRC(st->clock_sel) | in ad7192_setup()
371 st->conf = AD7192_CONF_GAIN(0); in ad7192_setup()
375 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
378 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
379 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
381 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
382 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_setup()
386 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
390 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
395 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
397 dev_warn(&st->sd.spi->dev, in ad7192_setup()
401 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
405 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
409 ret = ad7192_calibrate_all(st); in ad7192_setup()
414 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
415 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
417 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); in ad7192_setup()
420 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
421 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
432 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_ac_excitation() local
434 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); in ad7192_show_ac_excitation()
442 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_bridge_switch() local
444 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); in ad7192_show_bridge_switch()
453 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set() local
469 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
471 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
473 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
477 st->mode |= AD7192_MODE_ACX; in ad7192_set()
479 st->mode &= ~AD7192_MODE_ACX; in ad7192_set()
481 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set()
492 static void ad7192_get_available_filter_freq(struct ad7192_state *st, in ad7192_get_available_filter_freq() argument
498 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
499 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
502 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
503 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
504 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_get_available_filter_freq()
506 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
516 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_filter_avail() local
520 ad7192_get_available_filter_freq(st, freq_avail); in ad7192_show_filter_avail()
527 buf[len - 1] = '\n'; in ad7192_show_filter_avail()
569 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, in ad7192_set_3db_filter_freq() argument
579 ad7192_get_available_filter_freq(st, freq_avail); in ad7192_set_3db_filter_freq()
591 st->f_order = AD7192_SYNC4_FILTER; in ad7192_set_3db_filter_freq()
592 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
594 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
596 case 1: in ad7192_set_3db_filter_freq()
597 st->f_order = AD7192_SYNC3_FILTER; in ad7192_set_3db_filter_freq()
598 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
600 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
603 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
604 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
606 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
609 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
610 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
612 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
616 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
620 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
623 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) in ad7192_get_3db_filter_freq() argument
627 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_3db_filter_freq()
628 st->f_order * AD7192_MODE_RATE(st->mode)); in ad7192_get_3db_filter_freq()
630 if (st->conf & AD7192_CONF_CHOP) in ad7192_get_3db_filter_freq()
632 if (st->mode & AD7192_MODE_SINC3) in ad7192_get_3db_filter_freq()
644 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_raw() local
645 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); in ad7192_read_raw()
653 mutex_lock(&st->lock); in ad7192_read_raw()
654 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; in ad7192_read_raw()
655 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; in ad7192_read_raw()
656 mutex_unlock(&st->lock); in ad7192_read_raw()
667 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
675 *val = st->fclk / in ad7192_read_raw()
676 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); in ad7192_read_raw()
679 *val = ad7192_get_3db_filter_freq(st); in ad7192_read_raw()
693 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_raw() local
704 mutex_lock(&st->lock); in ad7192_write_raw()
705 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
706 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
708 tmp = st->conf; in ad7192_write_raw()
709 st->conf &= ~AD7192_CONF_GAIN(-1); in ad7192_write_raw()
710 st->conf |= AD7192_CONF_GAIN(i); in ad7192_write_raw()
711 if (tmp == st->conf) in ad7192_write_raw()
713 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
714 3, st->conf); in ad7192_write_raw()
715 ad7192_calibrate_all(st); in ad7192_write_raw()
718 mutex_unlock(&st->lock); in ad7192_write_raw()
726 div = st->fclk / (val * st->f_order * 1024); in ad7192_write_raw()
727 if (div < 1 || div > 1023) { in ad7192_write_raw()
732 st->mode &= ~AD7192_MODE_RATE(-1); in ad7192_write_raw()
733 st->mode |= AD7192_MODE_RATE(div); in ad7192_write_raw()
734 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
737 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); in ad7192_write_raw()
769 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_avail() local
773 *vals = (int *)st->scale_avail; in ad7192_read_avail()
776 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
806 .differential = ((_channel2) == -1 ? 0 : 1), \
807 .indexed = 1, \
834 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
838 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
842 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
845 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
846 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
849 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
857 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
858 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
863 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
895 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_channels_config() local
897 switch (st->chip_info->chip_id) { in ad7192_channels_config()
913 struct ad7192_state *st; in ad7192_probe() local
922 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in ad7192_probe()
926 st = iio_priv(indio_dev); in ad7192_probe()
928 mutex_init(&st->lock); in ad7192_probe()
930 st->avdd = devm_regulator_get(&spi->dev, "avdd"); in ad7192_probe()
931 if (IS_ERR(st->avdd)) in ad7192_probe()
932 return PTR_ERR(st->avdd); in ad7192_probe()
934 ret = regulator_enable(st->avdd); in ad7192_probe()
940 st->dvdd = devm_regulator_get(&spi->dev, "dvdd"); in ad7192_probe()
941 if (IS_ERR(st->dvdd)) { in ad7192_probe()
942 ret = PTR_ERR(st->dvdd); in ad7192_probe()
946 ret = regulator_enable(st->dvdd); in ad7192_probe()
952 voltage_uv = regulator_get_voltage(st->avdd); in ad7192_probe()
955 st->int_vref_mv = voltage_uv / 1000; in ad7192_probe()
963 st->chip_info = of_device_get_match_data(&spi->dev); in ad7192_probe()
964 indio_dev->name = st->chip_info->name; in ad7192_probe()
971 if (st->chip_info->chip_id == CHIPID_AD7195) in ad7192_probe()
976 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); in ad7192_probe()
982 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_probe()
984 st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk"); in ad7192_probe()
985 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) { in ad7192_probe()
986 ret = PTR_ERR(st->mclk); in ad7192_probe()
990 st->clock_sel = ad7192_of_clock_select(st); in ad7192_probe()
992 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || in ad7192_probe()
993 st->clock_sel == AD7192_CLK_EXT_MCLK2) { in ad7192_probe()
994 ret = clk_prepare_enable(st->mclk); in ad7192_probe()
998 st->fclk = clk_get_rate(st->mclk); in ad7192_probe()
999 if (!ad7192_valid_external_frequency(st->fclk)) { in ad7192_probe()
1007 ret = ad7192_setup(st, spi->dev.of_node); in ad7192_probe()
1017 clk_disable_unprepare(st->mclk); in ad7192_probe()
1021 regulator_disable(st->dvdd); in ad7192_probe()
1023 regulator_disable(st->avdd); in ad7192_probe()
1031 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_remove() local
1034 clk_disable_unprepare(st->mclk); in ad7192_remove()
1037 regulator_disable(st->dvdd); in ad7192_remove()
1038 regulator_disable(st->avdd); in ad7192_remove()