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/qemu/include/hw/arm/
H A Dfsl-imx25.h74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
84 * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
85 * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
86 * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
87 * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
89 * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
90 * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
91 * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc5 F2(RI_a, R(1, 8), I(2,16,16))
6 F2(RI_b, R(1, 8), I(2,16,16))
7 F2(RI_c, M(1, 8), I(2,16,16))
8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
[all …]
H A Dvec_string_helper.c39 * Returns the byte offset for the first match, or 16 for no match.
84 uint64_t first_zero = 16; in vfae()
126 if (first_zero == 16 && first_equal == 16) { in vfae()
128 } else if (first_zero == 16) { in vfae()
147 DEF_VFAE_HELPER(16)
161 DEF_VFAE_CC_HELPER(16)
168 uint64_t first_zero = 16; in vfee()
187 if (first_zero == 16 && first_equal == 16) { in vfee()
189 } else if (first_zero == 16) { in vfee()
206 DEF_VFEE_HELPER(16)
[all …]
/qemu/hw/audio/
H A Dgustate.h43 #define VSRegsEnd (VSRControl+VSRegs + 32*(16*2))
51 #define VSRVolRampEndVol (16)
61 #define wVSRegsEnd (wVSRControl+wVSRegs + 32*(16))
83 #define RegCtrl_2xF (VSRVolRampControl+2+(16*2))
84 #define Jumper_2xB (VSRVolRampControl+2+(16*2)+1)
85 #define GUS42DMAStart (VSRVolRampControl+2+(16*2)+2)
87 #define GUS43DRAMIOlo (VSRVolRampControl+2+(16*2)*2)
89 #define GUS44DRAMIOhi (VSRVolRampControl+2+(16*2)*2+2)
91 #define voicewavetableirq (VSRVolRampControl+2+(16*2)*3) /* voice IRQ pseudoqueue: 1 bit per voice …
93 #define voicevolrampirq (VSRVolRampControl+2+(16*2)*4) /* voice IRQ pseudoqueue: 1 bit per voice …
[all …]
/qemu/tests/tcg/aarch64/
H A Dtest-aes.c8 asm("ld1 { v0.16b }, [%1]\n\t" in test_SB_SR()
9 "movi v1.16b, #0\n\t" in test_SB_SR()
10 "aese v0.16b, v1.16b\n\t" in test_SB_SR()
11 "st1 { v0.16b }, [%0]" in test_SB_SR()
18 asm("ld1 { v0.16b }, [%1]\n\t" in test_MC()
19 "aesmc v0.16b, v0.16b\n\t" in test_MC()
20 "st1 { v0.16b }, [%0]" in test_MC()
33 asm("ld1 { v0.16b }, [%1]\n\t" in test_ISB_ISR()
34 "movi v1.16b, #0\n\t" in test_ISB_ISR()
35 "aesd v0.16b, v1.16b\n\t" in test_ISB_ISR()
[all …]
/qemu/tests/qemu-iotests/
H A D049.out7 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
10 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
13 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
16 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
19 …r_size=65536 extended_l2=off compression_type=zlib size=1048576 lazy_refcounts=off refcount_bits=16
22 …ize=65536 extended_l2=off compression_type=zlib size=1073741824 lazy_refcounts=off refcount_bits=16
25 …=65536 extended_l2=off compression_type=zlib size=1099511627776 lazy_refcounts=off refcount_bits=16
28 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
31 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
34 …ster_size=65536 extended_l2=off compression_type=zlib size=1536 lazy_refcounts=off refcount_bits=16
[all …]
/qemu/tests/tcg/alpha/system/
H A Dboot.S53 mov $gp, $16
57 ldah $16, entInt($gp) !gprelhigh
58 lda $16, entInt($16) !gprellow
62 ldah $16, entArith($gp) !gprelhigh
63 lda $16, entArith($16) !gprellow
67 ldah $16, entMM($gp) !gprelhigh
68 lda $16, entMM($16) !gprellow
72 ldah $16, entIF($gp) !gprelhigh
73 lda $16, entIF($16) !gprellow
77 ldah $16, entUna($gp) !gprelhigh
[all …]
/qemu/target/arm/tcg/
H A Dneon_helper.c210 (dest = do_uqrshl_bhs(src1, (int8_t)src2, 16, false, NULL))
215 (dest = do_sqrshl_bhs(src1, (int8_t)src2, 16, false, NULL))
226 (dest = do_sqrshl_bhs(src1, (int8_t)src2, 16, true, NULL))
258 (dest = do_uqrshl_bhs(src1, (int8_t)src2, 16, true, NULL)) in NEON_GVEC_VOP2()
291 (dest = do_uqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) in NEON_GVEC_VOP2_ENV()
327 (dest = do_sqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) in NEON_GVEC_VOP2_ENV()
362 (dest = do_suqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) in NEON_GVEC_VOP2i_ENV()
394 (dest = do_uqrshl_bhs(src1, (int8_t)src2, 16, true, env->vfp.qc)) in NEON_GVEC_VOP2i_ENV()
426 (dest = do_sqrshl_bhs(src1, (int8_t)src2, 16, true, env->vfp.qc)) in NEON_GVEC_VOP2_ENV()
497 for (n = 16; x; n--) in do_clz16()
[all …]
H A Dop_addsub.c.inc29 ADD16(a >> 16, b >> 16, 1);
41 ADD8(a >> 16, b >> 16, 2);
53 SUB16(a >> 16, b >> 16, 1);
65 SUB8(a >> 16, b >> 16, 2);
76 ADD16(a, b >> 16, 0);
77 SUB16(a >> 16, b, 1);
87 SUB16(a, b >> 16, 0);
88 ADD16(a >> 16, b, 1);
H A Diwmmxt_helper.c31 /* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
34 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
61 EXTEND16S((a >> 16) & 0xffff) * EXTEND16S((b >> 16) & 0xffff) in HELPER()
73 ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff) in HELPER()
86 SADB(0) + SADB(8) + SADB(16) + SADB(24) + in HELPER()
95 return SADW(0) + SADW(16) + SADW(32) + SADW(48); in HELPER()
104 return MULS(0) | MULS(16) | MULS(32) | MULS(48); in HELPER()
112 ) >> 16) & 0xffff) << SHR) in HELPER()
113 return MULS(0) | MULS(16) | MULS(32) | MULS(48); in HELPER()
122 return MULU(0) | MULU(16) | MULU(32) | MULU(48); in HELPER()
[all …]
/qemu/tests/unit/
H A Dtest-smp-parse.c170 /* config: -smp maxcpus=16
171 * prefer_sockets: cpus=16,sockets=16,cores=1,threads=1,maxcpus=16
172 * prefer_cores: cpus=16,sockets=1,cores=16,threads=1,maxcpus=16 */
173 .config = SMP_CONFIG_GENERIC(F, 0, F, 0, F, 0, F, 0, T, 16),
174 .expect_prefer_sockets = CPU_TOPOLOGY_GENERIC(16, 16, 1, 1, 16),
175 .expect_prefer_cores = CPU_TOPOLOGY_GENERIC(16, 1, 16, 1, 16),
196 /* config: -smp 8,maxcpus=16
197 * prefer_sockets: cpus=8,sockets=16,cores=1,threads=1,maxcpus=16
198 * prefer_cores: cpus=8,sockets=1,cores=16,threads=1,maxcpus=16 */
199 .config = SMP_CONFIG_GENERIC(T, 8, F, 0, F, 0, F, 0, T, 16),
[all …]
H A Dtest-crypto-ivgen.c44 .niv = 16,
53 .niv = 16,
62 .niv = 16,
71 .niv = 16,
80 .niv = 16,
89 .niv = 16,
100 .nkey = 16,
103 .niv = 16,
114 .nkey = 16,
117 .niv = 16,
[all …]
/qemu/hw/usb/
H A Dhcd-dwc3.c51 FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
75 FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
86 FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
94 FIELD(GCTL, U2RSTECN, 16, 1)
124 FIELD(GGPIO, GPO, 16, 16)
125 FIELD(GGPIO, GPI, 0, 16)
132 FIELD(GUCTL, RESBWHSEPS, 16, 1)
144 FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
195 FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
200 FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
[all …]
/qemu/target/hppa/
H A Dop_helper.c117 cpu_stb_data_ra(env, addr, val >> 16, ra); in do_stby_b()
142 cpu_stb_data_ra(env, addr, val >> 16, ra); in do_stdby_b()
214 cpu_stw_data_ra(env, addr - 3, val >> 16, ra); in do_stby_e()
219 cpu_stw_data_ra(env, addr - 2, val >> 16, ra); in do_stby_e()
243 cpu_stw_data_ra(env, addr - 3, val >> 16, ra); in do_stdby_e()
254 cpu_stw_data_ra(env, addr - 2, val >> 16, ra); in do_stdby_e()
319 "Undefined ldc to unaligned address mod 16: " in HELPER()
371 for (int i = 0; i < 64; i += 16) { in HELPER()
372 int f1 = sextract64(r1, i, 16); in HELPER()
373 int f2 = sextract64(r2, i, 16); in HELPER()
[all …]
/qemu/target/tricore/
H A Dop_helper.c126 uint32_t incr = reg >> 16; in helper_br_update()
134 uint32_t length = reg >> 16; in helper_circ_update()
228 env->PSW_USB_AV = (av0 | av1) << 16; in ssov16()
230 return (hw0 & 0xffff) | (hw1 << 16); in ssov16()
258 env->PSW_USB_AV = (av0 | av1) << 16; in suov16()
260 return (hw0 & 0xffff) | (hw1 << 16); in suov16()
302 ret_hw0 = sextract32(r1, 0, 16) + sextract32(r2, 0, 16); in helper_add_h_ssov()
303 ret_hw1 = sextract32(r1, 16, 16) + sextract32(r2, 16, 16); in helper_add_h_ssov()
350 return (result1 & 0xffff0000ULL) | ((result0 >> 16) & 0xffffULL); in helper_addr_h_ssov()
396 return (result1 & 0xffff0000ULL) | ((result0 >> 16) & 0xffffULL); in helper_addsur_h_ssov()
[all …]
/qemu/target/mips/tcg/
H A Dmxu_translate.c58 * D - two operations in parallel 16 - half word
506 * MXU pool 16
680 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m()
685 } else if (XRa == 16) { in gen_mxu_s32i2m()
701 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i()
705 } else if (XRa == 16) { in gen_mxu_s32m2i()
750 /* XRa[23:16] = tmp8 */ in gen_mxu_s8ldd()
754 tcg_gen_deposit_tl(t0, t0, t1, 16, 8); in gen_mxu_s8ldd()
765 tcg_gen_deposit_tl(t0, t1, t1, 16, 16); in gen_mxu_s8ldd()
771 tcg_gen_deposit_tl(t0, t1, t1, 16, 16); in gen_mxu_s8ldd()
[all …]
/qemu/target/hexagon/
H A Dcpu.h57 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
58 MMVector data QEMU_ALIGNED(16);
95 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
96 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
97 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
99 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
100 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
103 MMVectorPair VuuV QEMU_ALIGNED(16);
104 MMVectorPair VvvV QEMU_ALIGNED(16);
105 MMVectorPair VxxV QEMU_ALIGNED(16);
[all …]
/qemu/crypto/
H A Dcipher.c29 [QCRYPTO_CIPHER_ALGO_AES_128] = 16,
34 [QCRYPTO_CIPHER_ALGO_CAST5_128] = 16,
35 [QCRYPTO_CIPHER_ALGO_SERPENT_128] = 16,
38 [QCRYPTO_CIPHER_ALGO_TWOFISH_128] = 16,
42 [QCRYPTO_CIPHER_ALGO_SM4] = 16,
47 [QCRYPTO_CIPHER_ALGO_AES_128] = 16,
48 [QCRYPTO_CIPHER_ALGO_AES_192] = 16,
49 [QCRYPTO_CIPHER_ALGO_AES_256] = 16,
53 [QCRYPTO_CIPHER_ALGO_SERPENT_128] = 16,
54 [QCRYPTO_CIPHER_ALGO_SERPENT_192] = 16,
[all …]
/qemu/linux-headers/asm-s390/
H A Dkvm.h57 #define KVM_S390_RESET_IPL 16
118 ((ssid) << 16) | \
189 __u8 fixed_logout[16];
448 __u64 feat[16];
456 __u8 ptff[16]; /* with TOD-clock steering */
457 __u8 kmac[16]; /* with MSA */
458 __u8 kmc[16]; /* with MSA */
459 __u8 km[16]; /* with MSA */
460 __u8 kimd[16]; /* with MSA */
461 __u8 klmd[16]; /* with MSA */
[all …]
/qemu/target/ppc/
H A Dinternal.h105 EXTRACT_HELPER(opc4, 16, 5);
115 EXTRACT_HELPER(rA, 16, 5);
125 EXTRACT_HELPER(crbA, 16, 5);
136 /* 16 bits signed immediate value */
137 EXTRACT_SHELPER(SIMM, 0, 16);
138 /* 16 bits unsigned immediate value */
139 EXTRACT_HELPER(UIMM, 0, 16);
141 EXTRACT_SHELPER(SIMM5, 16, 5);
143 EXTRACT_HELPER(UIMM5, 16, 5);
145 EXTRACT_HELPER(UIMM4, 16, 4);
[all …]
/qemu/tests/qtest/
H A Dvhost-user-blk-test.c90 qtest_memwrite(qts, addr, req, 16); in virtio_blk_request()
91 qtest_memwrite(qts, addr + 16, req->data, data_size); in virtio_blk_request()
92 qtest_memwrite(qts, addr + 16 + data_size, &status, sizeof(status)); in virtio_blk_request()
125 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_invalid_discard_write_zeroes()
126 qvirtqueue_add(qts, vq, req_addr + 16, sizeof(dwz_hdr2), false, true); in test_invalid_discard_write_zeroes()
127 qvirtqueue_add(qts, vq, req_addr + 16 + sizeof(dwz_hdr2), 1, true, in test_invalid_discard_write_zeroes()
134 status = readb(req_addr + 16 + sizeof(dwz_hdr2)); in test_invalid_discard_write_zeroes()
150 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_invalid_discard_write_zeroes()
151 qvirtqueue_add(qts, vq, req_addr + 16, sizeof(dwz_hdr), false, true); in test_invalid_discard_write_zeroes()
152 qvirtqueue_add(qts, vq, req_addr + 16 + sizeof(dwz_hdr), 1, true, in test_invalid_discard_write_zeroes()
[all …]
H A Dvirtio-blk-test.c106 memwrite(addr, req, 16); in virtio_blk_request()
107 memwrite(addr + 16, req->data, data_size); in virtio_blk_request()
108 memwrite(addr + 16 + data_size, &status, sizeof(status)); in virtio_blk_request()
152 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_basic()
153 qvirtqueue_add(qts, vq, req_addr + 16, 512, false, true); in test_basic()
175 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_basic()
176 qvirtqueue_add(qts, vq, req_addr + 16, 512, true, true); in test_basic()
187 memread(req_addr + 16, data, 512); in test_basic()
211 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_basic()
212 qvirtqueue_add(qts, vq, req_addr + 16, sizeof(dwz_hdr), false, true); in test_basic()
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_mac16.S37 assert_acc_value mul16(\a, (\b >> 16))
40 assert_acc_value mul16((\a >> 16), \b)
43 assert_acc_value mul16((\a >> 16), (\b >> 16))
80 assert_acc_value (\iv \op mul16(\a, (\b >> 16)))
84 assert_acc_value (\iv \op mul16((\a >> 16), \b))
88 assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16)))
176 assert_acc_value (\iv \op mul16(\a, (\b >> 16)))
180 assert_acc_value (\iv \op mul16((\a >> 16), \b))
184 assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16)))
219 movi a3, 1f - 16
[all …]
H A Dtest_lsc.S163 ldi f2, a2, 16
164 ldip f0, a2, 16
165 movi a3, 1f + 16
189 sdi f5, a2, 16
190 sdip f3, a2, 16
191 movi a3, 1f + 16
193 l32i a4, a2, -16 + F64_HIGH_OFF
213 movi a5, 16
217 movi a3, 1f + 16
242 movi a5, 16
[all …]
/qemu/target/loongarch/tcg/
H A Dvec_helper.c32 DO_ODD_EVEN(vhaddw_h_b, 16, H, B, DO_ADD)
44 for (i = 0; i < oprsz / 16 ; i++) { in HELPER()
50 DO_ODD_EVEN(vhsubw_h_b, 16, H, B, DO_SUB)
62 for (i = 0; i < oprsz / 16; i++) { in HELPER()
68 DO_ODD_EVEN(vhaddw_hu_bu, 16, UH, UB, DO_ADD)
80 for (i = 0; i < oprsz / 16; i ++) { in HELPER()
86 DO_ODD_EVEN(vhsubw_hu_bu, 16, UH, UB, DO_SUB)
98 for (i = 0; i < oprsz / 16; i++) { in HELPER()
142 for (i = 0; i < oprsz / 16; i++) { in HELPER()
148 DO_EVEN(vaddwev_h_b, 16, H, B, DO_ADD)
[all …]

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