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/qemu/net/can/
H A Dcan_core.c56 14, 14, 14, 14, 14, 14, 14, 14, /* 33 - 40 */
57 14, 14, 14, 14, 14, 14, 14, 14, /* 41 - 48 */
/qemu/hw/net/
H A Dtulip.h20 #define CSR0_CAC_SHIFT 14
46 #define CSR5_ERI BIT(14)
98 #define CSR6_TR_SHIFT 14
122 #define CSR7_ERM BIT(14)
138 #define CSR9_RD BIT(14)
182 #define CSR14_SPP BIT(14)
199 #define CSR15_LE2 BIT(14)
215 #define RDES0_DE BIT(14)
240 #define TDES0_TO BIT(14)
H A Dvmxnet3.h232 u32 msscof:14; /* MSS, checksum offset, flags */
237 u32 len:14;
239 u32 len:14;
244 u32 msscof:14; /* MSS, checksum offset, flags */
282 #define VMXNET3_TXD_GEN_SHIFT 14
344 u32 len:14;
346 u32 len:14;
363 #define VMXNET3_RXD_BTYPE_SHIFT 14
400 u32 len:14; /* data length */
402 u32 len:14; /* data length */
[all …]
/qemu/common-user/host/ppc64/
H A Dsafe-syscall.inc.S49 std 14, 16(1) /* Preserve r14 in SP+16 */
50 .cfi_offset 14, 16
51 mr 14, 3 /* signal_pending */
69 lwz 12, 0(14)
75 ld 14, 16(1) /* restore r14 */
80 2: ld 14, 16(1) /* restore r14 */
/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c91 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14; in pnv_pbcq_update_map()
93 size = ((~mask) >> 14) + 1; in pnv_pbcq_update_map()
101 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14; in pnv_pbcq_update_map()
103 size = ((~mask) >> 14) + 1; in pnv_pbcq_update_map()
111 bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14; in pnv_pbcq_update_map()
250 pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] = mm0 << 14; in pnv_pbcq_default_bars()
251 pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] = mm1 << 14; in pnv_pbcq_default_bars()
252 pbcq->nest_regs[PBCQ_NEST_PHB_BAR] = reg << 14; in pnv_pbcq_default_bars()
253 pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14; in pnv_pbcq_default_bars()
254 pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14; in pnv_pbcq_default_bars()
[all …]
/qemu/target/arm/
H A Ddebug_helper.c117 spd = extract32(env->cp15.mdcr_el3, 14, 2); in aa32_generate_debug_exceptions()
951 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
958 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
963 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
983 { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
987 { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
992 { .name = "DBGDTR_EL0", .state = ARM_CP_STATE_BOTH, .cp = 14,
1001 { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
1012 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
1017 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
[all …]
/qemu/.gitlab-ci.d/
H A Dcirrus.yml34 x64-freebsd-14-build:
37 NAME: freebsd-14
40 CIRRUS_VM_IMAGE_NAME: freebsd-14-2
51 NAME: macos-14
/qemu/include/
H A Delf.h228 #define DT_SONAME 14
324 #define AT_EGID 14 /* effective gid */
400 #define R_MIPS_UNUSED2 14
465 #define R_SPARC_GOT13 14
510 #define HWCAP_ARM_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */
613 #define HWCAP_S390_NR_GS 14
692 #define R_68K_PLT16 14
762 #define R_PPC_GOT16 14
851 #define R_ARM_THM_SWI8 14
1020 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_wrdsp.c19 (efi_i << 14) | \ in main()
33 efi_o = (dsp_o >> 14) & 0x01; in main()
34 c_o = (dsp_o >> 14) & 0x01; in main()
H A Dtest_dsp_r1_rddsp.c19 (efi_i << 14) | \ in main()
33 efi_o = (dsp_o >> 14) & 0x01; in main()
34 c_o = (dsp_o >> 14) & 0x01; in main()
H A Dtest_dsp_r1_extp.c23 dsp = (dsp >> 14) & 0x01; in main()
40 dsp = (dsp >> 14) & 0x01; in main()
57 dsp = (dsp >> 14) & 0x01; in main()
/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref74 …fff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
75 res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0)
76 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
78 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + …
80 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
82 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
83 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1)
84 …0000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
85 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2)
86 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
[all …]
/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref74 …fff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
75 res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0)
76 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
78 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + …
80 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
82 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
83 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1)
84 …0000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
85 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2)
86 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
[all …]
H A Dfcvt.ref32 14 SINGLE: 6.10351999057456851006e-05 / 0x38800006 (0 => OK)
33 14 HALF: 0x400 (0x10 => INEXACT )
95 14 SINGLE: 6.10351999057456851006e-05 / 0x38800006 (0 => OK)
96 14 DOUBLE: 6.10351999057456851006e-05 / 0x003f100000c0000000 (0 => OK)
158 14 DOUBLE: 2.98023224000000013061e-08 / 0x003e600000001c5f68 (0 => OK)
159 14 HALF: 0x01 (0x18 => UNDERFLOW INEXACT )
241 14 DOUBLE: 2.98023224000000013061e-08 / 0x003e600000001c5f68 (0 => OK)
242 14 SINGLE: 2.98023223876953125000e-08 / 0x33000000 (0x10 => INEXACT )
324 14 HALF: 0x7c01 (0 => OK)
325 14 SINGLE: nan / 0x7fc02000 (0x1 => INVALID)
[all …]
/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref74 …fff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
75 res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0)
76 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
78 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + …
80 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
82 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
83 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1)
84 …0000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
85 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2)
86 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
[all …]
/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref74 …fff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
75 res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0)
76 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
78 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + …
80 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
82 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
83 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1)
84 …0000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
85 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2)
86 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
[all …]
/qemu/tests/tcg/arm/
H A Dfloat_madds.ref74 …fff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
75 res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0)
76 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
78 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + …
80 op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + …
82 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
83 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1)
84 …0000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006)
85 res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2)
86 op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f…
[all …]
H A Dfcvt.ref32 14 SINGLE: 6.10351999057456851006e-05 / 0x38800006 (0 => OK)
33 14 HALF: 0x400 (0x10 => INEXACT )
95 14 SINGLE: 6.10351999057456851006e-05 / 0x38800006 (0 => OK)
96 14 DOUBLE: 6.10351999057456851006e-05 / 0x003f100000c0000000 (0 => OK)
158 14 DOUBLE: 2.98023224000000013061e-08 / 0x003e600000001c5f68 (0 => OK)
159 14 HALF: 0000 (0x10 => INEXACT )
241 14 DOUBLE: 2.98023224000000013061e-08 / 0x003e600000001c5f68 (0 => OK)
242 14 SINGLE: 2.98023223876953125000e-08 / 0x33000000 (0x10 => INEXACT )
324 14 HALF: 0x7c01 (0 => OK)
325 14 SINGLE: nan / 0x7fc02000 (0x1 => INVALID)
[all …]
/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h77 #define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
81 #define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14, 55)
85 #define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14)
89 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46)
92 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14, 50)
98 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14, 51)
328 #define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14)
419 #define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14)
/qemu/include/hw/i2c/
H A Daspeed_i2c.h81 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1)
99 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1)
125 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1)
175 /* 14:0 shared with I2CD_INTR_STS[14:0] */
199 /* 14:0 shared with I2CD_INTR_STS[14:0] */
206 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1)
/qemu/tests/tcg/mips/
H A Dhello-mips.c28 : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", in exit1()
49 : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", in write()
62 write (1, "Hello, World!\n", 14); in __start()
/qemu/linux-headers/asm-arm/
H A Dkvm.h180 #define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
181 #define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
182 #define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
185 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
186 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
187 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
/qemu/include/hw/usb/
H A Ddwc2-regs.h158 #define GINTSTS_ISOUTDROP BIT(14)
251 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
252 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
288 #define GHWCFG3_BC_SUPPORT BIT(14)
315 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
316 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
370 #define GPWRDN_CONNECT_DET_MSK BIT(14)
417 #define GREFCLK_REF_CLK_MODE BIT(14)
585 #define DXEPINT_NYETINTRPT BIT(14)
658 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
[all …]
/qemu/tests/qtest/
H A Dtpm-util.c98 /* skip pcrUpdateCounter (14th byte) in comparison */ in tpm_util_pcrread()
101 g_assert_cmpmem(&buffer[14], exp_resp_size - 14, in tpm_util_pcrread()
102 &exp_resp[14], exp_resp_size - 14); in tpm_util_pcrread()
/qemu/gdb-xml/
H A Di386-32bit.xml21 <field name="NT" start="14" end="14"/>
104 <field name="SMXE" start="14" end="14"/>
115 <field name="FFXSR" start="14" end="14"/>

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