/qemu/target/hexagon/imported/mmvec/ |
H A D | encode_ext.def | 102 OP(TAGPRE##_cur_npred, 100,vv,101,ddddd) \ 103 OP(TAGPRE##_nt_cur_npred, 110,vv,101,ddddd) \ 205 DEF_ENC(V6_vaddcarrysat, ICLASS_CJ" 1 101 100 vvvvv PP 1 uuuuu 0ss ddddd") // 206 DEF_ENC(V6_vaddcarryo, ICLASS_CJ" 1 101 101 vvvvv PP 1 uuuuu 0ee ddddd") // 207 DEF_ENC(V6_vsubcarryo, ICLASS_CJ" 1 101 101 vvvvv PP 1 uuuuu 1ee ddddd") // 208 DEF_ENC(V6_vsatdw, ICLASS_CJ" 1 101 100 vvvvv PP 1 uuuuu 111 ddddd") // 217 DEF_ENC(V6_vgathermhq, ICLASS_NCJ" 1 111 000 ttttt PP u --101 -ss vvvvv") // if (Qs4) vt… 227 DEF_ENC(V6_vscattermh_add, ICLASS_NCJ" 1 111 001 ttttt PP u vvvvv 101 wwwww") // vmem(Rt32,M… 233 DEF_ENC(V6_vscattermhwq, ICLASS_NCJ" 1 111 101 ttttt PP u vvvvv 0ss wwwww") // if (Qs4) vmem… 258 DEF_ENC(V6_vasruhubsat, ICLASS_CJ" 1 000 vvv vvttt PP 1 uuuuu 101 ddddd") // [all …]
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/qemu/target/arm/tcg/ |
H A D | sve.decode | 304 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 312 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 348 URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr 356 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 369 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 370 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 371 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 372 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 373 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 374 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn [all …]
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H A D | a32-uncond.decode | 33 BLX_i 1111 101 . ........................ &i imm=%imm24h 60 PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te 62 PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 64 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te 66 PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
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H A D | a64.decode | 232 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 246 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 280 MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 308 # DCPS1 1101 0100 101 ................ 000 01 @i16 309 # DCPS2 1101 0100 101 ................ 000 10 @i16 310 # DCPS3 1101 0100 101 ................ 000 11 @i16 353 STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 354 LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 355 STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 356 LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 [all …]
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H A D | vfp-uncond.decode | 23 # 1111 1110 .... .... .... 101. ...0 .... 25 # 1111 110. .... .... .... 101. .... .... 26 # 1111 1110 .... .... .... 101. .... ....
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/qemu/target/riscv/ |
H A D | xthead.decode | 140 th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc 141 th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc 142 th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc 143 th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc 144 th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc 145 th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc 146 th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc 147 th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc 156 th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx 157 th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx [all …]
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H A D | insn32.decode | 138 bge ....... ..... ..... 101 ..... 1100011 @b 145 lhu ............ ..... 101 ..... 0000011 @i 157 srli 00000. ...... ..... 101 ..... 0010011 @sh 158 srai 01000. ...... ..... 101 ..... 0010011 @sh 165 srl 0000000 ..... ..... 101 ..... 0110011 @r 166 sra 0100000 ..... ..... 101 ..... 0110011 @r 179 csrrwi ............ ..... 101 ..... 1110011 @csr 189 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 190 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 194 srlw 0000000 ..... ..... 101 ..... 0111011 @r [all …]
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H A D | insn16.decode | 124 sq 101 ... ... .. ... 00 @cs_q 125 c_fsd 101 ... ... .. ... 00 @cs_d 159 jal 101 ........... 01 @cj rd=0 # C.J 193 sq 101 ... ... .. ... 10 @c_sqsp 194 c_fsd 101 ...... ..... 10 @c_sdsp 198 cm_push 101 11000 .... .. 10 @cm_pp 199 cm_pop 101 11010 .... .. 10 @cm_pp 200 cm_popret 101 11110 .... .. 10 @cm_pp 201 cm_popretz 101 11100 .... .. 10 @cm_pp 202 cm_mva01s 101 011 ... 11 ... 10 @cm_mv [all …]
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/qemu/target/hexagon/imported/ |
H A D | encode_subinsn.def | 50 DEF_ENC_SUBINSN(SL2_return_f, SUBINSN_L2, "111 1101---101") 56 DEF_ENC_SUBINSN(SL2_jumpr31_f, SUBINSN_L2, "111 1111---101") 89 DEF_ENC_SUBINSN(SA1_sxth, SUBINSN_A, "101 00ssssdddd") 90 DEF_ENC_SUBINSN(SA1_sxtb, SUBINSN_A, "101 01ssssdddd") 91 DEF_ENC_SUBINSN(SA1_zxth, SUBINSN_A, "101 10ssssdddd") 92 DEF_ENC_SUBINSN(SA1_zxtb, SUBINSN_A, "101 11ssssdddd") 99 DEF_ENC_SUBINSN(SA1_clrfnew, SUBINSN_A, "110 1--101dddd") 142 DEF_PACKED32(P2_PACKED_S1_S1, SUBINSN_S1, SUBINSN_S1, "101B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") 143 DEF_PACKED32(P2_PACKED_S1_S2, SUBINSN_S2, SUBINSN_S1, "101B BBBB BBBB BBBB EE1A AAAA AAAA AAAA")
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H A D | encode_pp.def | 110 STD_PST_IOENC(rbnew, "101","00ttt") 111 STD_PST_IOENC(rhnew, "101","01ttt") 112 STD_PST_IOENC(rinew, "101","10ttt") 143 STD_ST_GP(rbnew,"101","00ttt") 144 STD_ST_GP(rhnew,"101","01ttt") 145 STD_ST_GP(rinew,"101","10ttt") 163 DEF_CLASS32(ICLASS_V4LDST" 101- -------- PP------ --------",RplusR) 198 STD_PST_RRENC(rbnew, "101","00ttt") 199 STD_PST_RRENC(rhnew, "101","01ttt") 200 STD_PST_RRENC(rinew, "101","10ttt") [all …]
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/qemu/tests/tcg/s390x/ |
H A D | div.c | 8 int32_t b = 101, q, r; in test_dr() 24 uint32_t b = 101, q, r; in test_dlr() 40 int64_t b = 101, q, r; in test_dsgr() 56 uint64_t b = 101, q, r; in test_dlgr()
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/qemu/target/mips/tcg/ |
H A D | msa.decode | 73 MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 79 CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 88 BNEGI 011110 101 ....... ..... ..... 001001 @bit 102 BNEG 011110 101.. ..... ..... ..... 001101 @3r 111 MIN_U 011110 101.. ..... ..... ..... 001110 @3r 119 CLE_U 011110 101.. ..... ..... ..... 001111 @3r 126 AVE_U 011110 101.. ..... ..... ..... 010000 @3r 135 ASUB_U 011110 101.. ..... ..... ..... 010001 @3r 141 DIV_U 011110 101.. ..... ..... ..... 010010 @3r 150 DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r [all …]
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/qemu/hw/timer/ |
H A D | imx_gpt.c | 80 CLK_32k, /* 101 ipg_clk_32k */ 91 CLK_NONE, /* 101 not defined */ 102 CLK_HIGH_DIV, /* 101 reference clock / 8 */ 113 CLK_NONE, /* 101 not defined */ 124 CLK_HIGH, /* 101 reference clock */ 135 CLK_HIGH, /* 101 ipg_clk_16M */
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/qemu/target/hppa/ |
H A D | insns.decode | 448 bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 504 frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 511 frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 518 frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 525 frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 572 fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 573 fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 574 fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 575 fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 577 fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 [all …]
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/qemu/tests/unit/ |
H A D | test-qdev-global-props.c | 240 { TYPE_DYNAMIC_PROPS, "prop1", "101", }, in test_dynamic_globalprop_subprocess() 255 g_assert_cmpuint(mt->prop1, ==, 101); in test_dynamic_globalprop_subprocess() 289 { TYPE_STATIC_PROPS, "prop1", "101" }, in test_subclass_global_props()
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H A D | test-qdist.c | 266 [8] = { 0.0, 101, 1 }, in test_bin_expand() 290 [0] = { 10, 101, 8 }, in test_bin_simple() 295 [0] = { 0, 101, 8 }, in test_bin_simple()
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H A D | test-qht.c | 204 rm(101, 102); in qht_do_test() 210 insert(101, 102); in qht_do_test()
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/qemu/tests/qemu-iotests/ |
H A D | 101.out | 1 QA output created by 101
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H A D | 046 | 153 aio_write -P 101 0xaa000 0xe000 248 echo read -P 101 0xaa000 0xe000
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H A D | 048.out | 37 === IO: pattern 101
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/qemu/linux-user/alpha/ |
H A D | target_syscall.h | 52 #define TARGET_GSI_GET_HWRPB 101
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/qemu/tests/tcg/mips/user/isa/r5900/ |
H A D | test_r5900_divu1.c | 45 verify_divu1(77773, 101, 770, 3); in main()
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/qemu/linux-user/loongarch64/ |
H A D | syscall.tbl | 129 101 time32 nanosleep sys_nanosleep_time32 130 101 64 nanosleep sys_nanosleep
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/qemu/linux-user/hexagon/ |
H A D | syscall.tbl | 129 101 time32 nanosleep sys_nanosleep_time32 130 101 64 nanosleep sys_nanosleep
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/qemu/linux-user/riscv/ |
H A D | syscall.tbl | 129 101 time32 nanosleep sys_nanosleep_time32 130 101 64 nanosleep sys_nanosleep
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