Searched +full:0 +full:xf0000 (Results 1 – 25 of 151) sorted by relevance
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_5_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| D | oss_2_0_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
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| D | oss_3_0_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| D | oss_3_0_1_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| /linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/ |
| D | dma0_qm_masks.h | 23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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| D | mme0_qm_masks.h | 23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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| D | tpc0_qm_masks.h | 23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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| /linux-5.10/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phyreg.h | 11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
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| D | gmc_8_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
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| /linux-5.10/drivers/gpu/drm/sun4i/ |
| D | sun8i_csc.h | 14 #define CCSC00_OFFSET 0xAA050
15 #define CCSC01_OFFSET 0xFA050
16 #define CCSC10_OFFSET 0xA0000
17 #define CCSC11_OFFSET 0xF0000
19 #define SUN8I_CSC_CTRL(base) (base + 0x0)
20 #define SUN8I_CSC_COEFF(base, i) (base + 0x10 + 4 * i)
22 #define SUN8I_CSC_CTRL_EN BIT(0)
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| /linux-5.10/arch/arm/boot/dts/ |
| D | armada-395.dtsi | 19 reg = <0x18000 0x20>;
24 reg = <0xa8000 0x2000>;
32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
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| /linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | qoriq-fman3-0-10g-0.dtsi | 3 * QorIQ FMan v3 10g port #0 device tree
11 cell-index = <0x10>;
13 reg = <0x90000 0x1000>;
18 cell-index = <0x30>;
20 reg = <0xb0000 0x1000>;
25 cell-index = <0x8>;
27 reg = <0xf0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xf1000 0x1000>;
38 pcsphy6: ethernet-phy@0 {
[all …]
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| /linux-5.10/drivers/misc/mei/ |
| D | hw-me-regs.h | 12 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
13 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
14 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
15 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
17 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
18 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
20 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
21 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
22 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
23 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /linux-5.10/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-soc.dtsi | 20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
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| /linux-5.10/drivers/infiniband/hw/efa/ |
| D | efa_regs_defs.h | 10 EFA_REGS_RESET_NORMAL = 0,
24 /* 0 base */
25 #define EFA_REGS_VERSION_OFF 0x0
26 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4
27 #define EFA_REGS_CAPS_OFF 0x8
28 #define EFA_REGS_AQ_BASE_LO_OFF 0x10
29 #define EFA_REGS_AQ_BASE_HI_OFF 0x14
30 #define EFA_REGS_AQ_CAPS_OFF 0x18
31 #define EFA_REGS_ACQ_BASE_LO_OFF 0x20
32 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24
[all …]
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| /linux-5.10/arch/x86/um/asm/ |
| D | mm_context.h | 38 ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
41 (((info)->base_addr & 0xff000000) | \
42 (((info)->base_addr & 0x00ff0000) >> 16) | \
43 ((info)->limit & 0xf0000) | \
50 0x7000)
53 (info)->base_addr == 0 && \
54 (info)->limit == 0 && \
55 (info)->contents == 0 && \
57 (info)->seg_32bit == 0 && \
58 (info)->limit_in_pages == 0 && \
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| /linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/ |
| D | otx2_reg.h | 17 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
18 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
19 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
20 #define RVU_PF_VF_BAR4_ADDR (0x10)
21 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
22 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
23 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
24 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
25 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
26 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_2_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
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| /linux-5.10/drivers/clk/imx/ |
| D | clk-imx8qxp-lpcg.h | 11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
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| /linux-5.10/drivers/gpu/drm/tegra/ |
| D | dpaux.h | 9 #define DPAUX_CTXSW 0x00
11 #define DPAUX_INTR_EN_AUX 0x01
12 #define DPAUX_INTR_AUX 0x05
16 #define DPAUX_INTR_PLUG_EVENT (1 << 0)
18 #define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2))
19 #define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2))
20 #define DPAUX_DP_AUXADDR 0x29
22 #define DPAUX_DP_AUXCTL 0x2d
31 #define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12)
33 #define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff)
[all …]
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| /linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-fman-0-10g-0.dtsi | 2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
60 interrupts = <101 2 0 0>;
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| D | qoriq-fman-1-10g-0.dtsi | 2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
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