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Searched +full:0 +full:xc0000000 (Results 1 – 25 of 81) sorted by relevance

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/qemu/tests/tcg/xtensa/
H A Dtest_phys_mem.S10 movi a2, 0xc0000003 /* PPN */
11 movi a3, 0xc0000004 /* VPN */
14 movi a2, 0xc0000000
17 movi a2, 0xc0000000 | XCHAL_SPANNING_WAY
20 movi a2, 0x20000000 | XCHAL_SPANNING_WAY
29 movi a2, 0x20000000
32 movi a2, 0x20000000
45 movi a2, 0x20000000
47 l32i a3, a2, 0
50 movi a2, 0x20000000
[all …]
/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/qemu/tests/multiboot/
H A Dmmap.out10 0x0 - 0x9fc00: type 1 [entry size: 20]
11 0x9fc00 - 0xa0000: type 2 [entry size: 20]
12 0xf0000 - 0x100000: type 2 [entry size: 20]
13 0x100000 - 0x7fe0000: type 1 [entry size: 20]
14 0x7fe0000 - 0x8000000: type 2 [entry size: 20]
15 0xfffc0000 - 0x100000000: type 2 [entry size: 20]
17 mmap start: 0x9000
18 mmap end: 0x9090
19 real mmap end: 0x9090
28 0x0 - 0x9fc00: type 1 [entry size: 20]
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_dpaq_sa_l_w.c7 int ach = 0, acl = 0; in main()
10 rs = 0x80000000; in main()
11 rt = 0x80000000; in main()
12 resulth = 0x7FFFFFFF; in main()
13 resultl = 0xFFFFFFFF; in main()
14 resultdsp = 0x01; in main()
16 ("mthi %0, $ac1\n\t" in main()
19 "mfhi %0, $ac1\n\t" in main()
25 dsp = (dsp >> 17) & 0x01; in main()
30 ach = 0x00000012; in main()
[all …]
/qemu/hw/misc/
H A Dimx6ul_ccm.c23 [CCM_CCR] = 0xf01fef80,
24 [CCM_CCDR] = 0xfffeffff,
25 [CCM_CSR] = 0xffffffff,
26 [CCM_CCSR] = 0xfffffef2,
27 [CCM_CACRR] = 0xfffffff8,
28 [CCM_CBCDR] = 0xc1f8e000,
29 [CCM_CBCMR] = 0xfc03cfff,
30 [CCM_CSCMR1] = 0x80700000,
31 [CCM_CSCMR2] = 0xe01ff003,
32 [CCM_CSCDR1] = 0xfe00c780,
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
167 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
168 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
169 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
183 #define XCHAL_ITLB_WAY0_SET 0
186 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
192 /* ITLB way set 0 (group of ways 0 thru 0): */
[all …]
/qemu/linux-user/m68k/
H A Dtarget_mman.h2 #define TASK_UNMAPPED_BASE 0xC0000000
4 #define ELF_ET_DYN_BASE 0xD0000000
/qemu/linux-user/arm/
H A Dtarget_mman.h5 * CONFIG_PAGE_OFFSET 0xC0000000 (default in Kconfig)
7 #define TASK_UNMAPPED_BASE 0x40000000
10 #define ELF_ET_DYN_BASE 0x00400000
/qemu/linux-user/microblaze/
H A Dtarget_mman.h5 * CONFIG_KERNEL_START 0xc0000000 (default in Kconfig)
7 #define TASK_UNMAPPED_BASE 0x48000000
10 #define ELF_ET_DYN_BASE 0x08000000
/qemu/linux-user/hexagon/
H A Dtarget_mman.h7 * PAGE_OFFSET 0xc0000000
9 #define TASK_UNMAPPED_BASE 0x40000000
12 #define ELF_ET_DYN_BASE 0x08000000
/qemu/linux-user/i386/
H A Dtarget_mman.h10 * CONFIG_PAGE_OFFSET 0xc0000000 (default in Kconfig)
12 #define TASK_UNMAPPED_BASE 0x40000000
15 #define ELF_ET_DYN_BASE 0x00400000
/qemu/hw/arm/
H A Dstrongarm.h7 #define SA_CS0 0x00000000
8 #define SA_CS1 0x08000000
9 #define SA_CS2 0x10000000
10 #define SA_CS3 0x18000000
11 #define SA_PCMCIA_CS0 0x20000000
12 #define SA_PCMCIA_CS1 0x30000000
13 #define SA_CS4 0x40000000
14 #define SA_CS5 0x48000000
16 #define SA_SDCS0 0xc0000000
17 #define SA_SDCS1 0xc8000000
[all …]
H A Dkzm.c31 * 0x00000000-0x7fffffff See i.MX31 SOC for support
32 * 0x80000000-0x8fffffff RAM EMULATED
33 * 0x90000000-0x9fffffff RAM EMULATED
34 * 0xa0000000-0xafffffff Flash IGNORED
35 * 0xb0000000-0xb3ffffff Unavailable IGNORED
36 * 0xb4000000-0xb4000fff 8-bit free space IGNORED
37 * 0xb4001000-0xb400100f Board control IGNORED
38 * 0xb4001003 DIP switch
39 * 0xb4001010-0xb400101f 7-segment LED IGNORED
40 * 0xb4001020-0xb400102f LED IGNORED
[all …]
H A Dimx25_pdk.c38 * 0x00000000-0x7fffffff See i.MX25 SOC fr support
39 * 0x80000000-0x87ffffff RAM + Alias EMULATED
40 * 0x90000000-0x9fffffff RAM + Alias EMULATED
41 * 0xa0000000-0xa7ffffff Flash IGNORED
42 * 0xa8000000-0xafffffff Flash IGNORED
43 * 0xb0000000-0xb1ffffff SRAM IGNORED
44 * 0xb2000000-0xb3ffffff SRAM IGNORED
45 * 0xb4000000-0xb5ffffff CS4 IGNORED
46 * 0xb6000000-0xb8000fff Reserved IGNORED
47 * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED
[all …]
/qemu/tests/qemu-iotests/
H A D215.out13 read 0/0 bytes at offset 0
14 0 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 2 GiB (0x80010000) bytes allocated at offset 0 bytes (0x0)
21 1023.938 MiB (0x3fff0000) bytes not allocated at offset 2 GiB (0x80010000)
22 64 KiB (0x10000) bytes allocated at offset 3 GiB (0xc0000000)
23 1023.938 MiB (0x3fff0000) bytes not allocated at offset 3 GiB (0xc0010000)
H A D197.out13 read 0/0 bytes at offset 0
14 0 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 2 GiB (0x80010000) bytes allocated at offset 0 bytes (0x0)
21 1023.938 MiB (0x3fff0000) bytes not allocated at offset 2 GiB (0x80010000)
22 64 KiB (0x10000) bytes allocated at offset 3 GiB (0xc0000000)
23 1023.938 MiB (0x3fff0000) bytes not allocated at offset 3 GiB (0xc0010000)
30 read 1024/1024 bytes at offset 0
32 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
39 wrote 65536/65536 bytes at offset 0
45 28 KiB (0x7000) bytes not allocated at offset 0 bytes (0x0)
[all …]
/qemu/linux-user/aarch64/
H A Dvdso.S13 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
14 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
45 svc #0
74 svc #0
/qemu/bsd-user/arm/
H A Dtarget_arch_vmparam.h33 #define TARGET_RESERVED_VA 0xf7000000
36 #define TARGET_VM_MAXUSER_ADDRESS (0xc0000000 - (512 * MiB))
/qemu/target/i386/hvf/
H A Dhvf-cpu.c27 hvf_get_supported_cpuid(0x0, 0, R_EAX); in hvf_cpu_max_instance_init()
29 hvf_get_supported_cpuid(0x80000000, 0, R_EAX); in hvf_cpu_max_instance_init()
31 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); in hvf_cpu_max_instance_init()
45 x86_ext_save_areas[XSTATE_FP_BIT].offset = 0; in hvf_cpu_xsave_init()
46 x86_ext_save_areas[XSTATE_SSE_BIT].offset = 0; in hvf_cpu_xsave_init()
52 int sz = hvf_get_supported_cpuid(0xd, i, R_EAX); in hvf_cpu_xsave_init()
53 if (sz != 0) { in hvf_cpu_xsave_init()
55 esa->offset = hvf_get_supported_cpuid(0xd, i, R_EBX); in hvf_cpu_xsave_init()
/qemu/hw/ppc/
H A Dmpc8544ds.c23 const char compatible[] = "MPC8544DS\0MPC85xxDS"; in mpc8544ds_fixup_devtree()
32 if (machine->ram_size > 0xc0000000) { in mpc8544ds_init()
45 pmc->pci_first_slot = 0x11; in mpc8544ds_machine_class_init()
49 pmc->platform_bus_base = 0xFF800000ULL; in mpc8544ds_machine_class_init()
53 pmc->ccsrbar_base = 0xE0000000ULL; in mpc8544ds_machine_class_init()
54 pmc->pci_mmio_base = 0xC0000000ULL; in mpc8544ds_machine_class_init()
55 pmc->pci_mmio_bus_base = 0xC0000000ULL; in mpc8544ds_machine_class_init()
56 pmc->pci_pio_base = 0xE1000000ULL; in mpc8544ds_machine_class_init()
57 pmc->spin_base = 0xEF000000ULL; in mpc8544ds_machine_class_init()
/qemu/linux-user/xtensa/
H A Dcpu_loop.c46 put_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_overflow4()
55 get_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_underflow4()
64 put_user_ual(env->regs[0], env->regs[9] - 16); in xtensa_overflow8()
65 get_user_ual(env->regs[0], env->regs[1] - 12); in xtensa_overflow8()
69 put_user_ual(env->regs[4], env->regs[0] - 32); in xtensa_overflow8()
70 put_user_ual(env->regs[5], env->regs[0] - 28); in xtensa_overflow8()
71 put_user_ual(env->regs[6], env->regs[0] - 24); in xtensa_overflow8()
72 put_user_ual(env->regs[7], env->regs[0] - 20); in xtensa_overflow8()
78 get_user_ual(env->regs[0], env->regs[9] - 16); in xtensa_underflow8()
92 put_user_ual(env->regs[0], env->regs[13] - 16); in xtensa_overflow12()
[all …]
/qemu/include/hw/i386/
H A Dmicrovm.h33 * 0 | pit |
37 * 4 | serial 0 | serial
47 * 14 | ide 0 | pcie
53 #define VIRTIO_MMIO_BASE 0xfeb00000
56 #define GED_MMIO_BASE 0xfea00000
57 #define GED_MMIO_BASE_MEMHP (GED_MMIO_BASE + 0x100)
58 #define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
61 #define MICROVM_XHCI_BASE 0xfe900000
64 #define PCIE_MMIO_BASE 0xc0000000
65 #define PCIE_MMIO_SIZE 0x20000000
[all …]
/qemu/target/alpha/
H A Dfpu_helper.c44 uint32_t ret = 0; in soft_to_fpcr_exc()
47 set_float_exception_flags(0, &FP_STATUS); in soft_to_fpcr_exc()
81 fp_exc_raise1(env, GETPC(), exc, regno, 0); in helper_fp_exc_raise()
112 uint32_t exp = (uint32_t)(val >> 52) & 0x7ff; in helper_ieee_input()
113 uint64_t frac = val & 0xfffffffffffffull; in helper_ieee_input()
115 if (exp == 0) { in helper_ieee_input()
117 if (frac != 0) { in helper_ieee_input()
118 arith_excp(env, GETPC(), EXC_M_INV, 0); in helper_ieee_input()
120 } else if (exp == 0x7ff) { in helper_ieee_input()
123 arith_excp(env, GETPC(), EXC_M_INV, 0); in helper_ieee_input()
[all …]
/qemu/hw/i386/
H A Dpc_piix.c75 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
76 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
96 for (i = 0; i < PIIX_NUM_PIRQS; i++) { in piix_intx_routing_notifier_xen()
98 const uint8_t v = route.mode == PCI_INTX_ENABLED ? route.irq : 0; in piix_intx_routing_notifier_xen()
120 uint64_t hole64_size = 0; in pc_init1()
126 * - Traditional split is 3.5G (lowmem = 0xe0000000). This is the in pc_init1()
130 * (lowmem = 0xc0000000). But only in case we have to split in in pc_init1()
158 pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */ in pc_init1()
163 if (lowmem > 0xc0000000) { in pc_init1()
164 lowmem = 0xc0000000; in pc_init1()
[all …]
/qemu/hw/microblaze/
H A Dboot.c85 return 0; in microblaze_load_dtb()
94 if (r < 0) { in microblaze_load_dtb()
114 return addr - 0x30000000LL; in translate_kernel_address()
148 EM_MICROBLAZE, 0, 0); in microblaze_load_kernel()
150 if (base32 == 0xc0000000) { in microblaze_load_kernel()
155 EM_MICROBLAZE, 0, 0); in microblaze_load_kernel()
161 if (kernel_size < 0) { in microblaze_load_kernel()
164 kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0, in microblaze_load_kernel()
171 if (kernel_size < 0) { in microblaze_load_kernel()
189 if (initrd_size < 0) { in microblaze_load_kernel()
[all …]

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