Lines Matching +full:0 +full:xc0000000
164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
167 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
168 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
169 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
183 #define XCHAL_ITLB_WAY0_SET 0
186 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
192 /* ITLB way set 0 (group of ways 0 thru 0): */
193 #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
197 #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
199 #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
204 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
205 #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index b…
206 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all…
207 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
208 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 other…
209 #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwi…
210 #define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwi…
211 #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise…
212 /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
213 #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
214 #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
215 #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
216 #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
217 #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
218 #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
219 #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
220 #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
221 /* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */
222 #define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000
223 #define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000
224 #define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000
225 #define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000
226 #define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000
227 #define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000
228 #define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000
229 #define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000
230 /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
231 #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
232 #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
233 #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
234 #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
235 #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
236 #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
237 #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
238 #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
243 #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
245 #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
249 #define XCHAL_DTLB_WAY0_SET 0
252 #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
255 #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
258 /* DTLB way set 0 (group of ways 0 thru 0): */
259 #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
263 #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
265 #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
270 #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
271 #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index b…
272 #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all…
273 #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
274 #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 other…
275 #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwi…
276 #define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwi…
277 #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise…
278 /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
279 #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
280 #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
281 #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
282 #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
283 #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
284 #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
285 #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
286 #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
287 /* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */
288 #define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000
289 #define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000
290 #define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000
291 #define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000
292 #define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000
293 #define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000
294 #define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000
295 #define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000
296 /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
297 #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
298 #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
299 #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
300 #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
301 #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
302 #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
303 #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
304 #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02