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12

/linux-5.10/drivers/net/mdio/
Dmdio-mvusb.c9 #define USB_MARVELL_VID 0x1286
12 { USB_DEVICE(USB_MARVELL_VID, 0x1fa4) },
40 mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0xa400 | (dev << 5) | reg); in mvusb_mdio_read()
63 mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0x8000 | (dev << 5) | reg); in mvusb_mdio_write()
86 mvusb->buf[MVUSB_CMD_PREAMBLE0] = cpu_to_le16(0xe800); in mvusb_mdio_probe()
87 mvusb->buf[MVUSB_CMD_PREAMBLE1] = cpu_to_le16(0x0001); in mvusb_mdio_probe()
/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_dbgdev.h37 CONTEXT_REG_BASE = 0xA000,
38 CONTEXT_REG_END = 0xA400,
44 USERCONFIG_REG_BASE = 0xC000,
45 USERCONFIG_REG_END = 0x10000,
51 AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */
52 AMD_CONFIG_REG_END = 0x2B00,
58 SH_REG_BASE = 0x2C00,
59 SH_REG_END = 0x3000,
64 #define SQ_CMD 0x8DEC
67 SQ_IND_CMD_CMD_NULL = 0x00000000,
[all …]
/linux-5.10/drivers/media/dvb-frontends/
Dstv6111.c46 { 2572, 0 },
82 { 1548, 0 },
118 { 4870, 0x3000 },
119 { 4850, 0x3C00 },
120 { 4800, 0x4500 },
121 { 4750, 0x4800 },
122 { 4700, 0x4B00 },
123 { 4650, 0x4D00 },
124 { 4600, 0x4F00 },
125 { 4550, 0x5100 },
[all …]
Dmxl5xx_regs.h23 #define HYDRA_INTR_STATUS_REG 0x80030008
24 #define HYDRA_INTR_MASK_REG 0x8003000C
26 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
27 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
29 #define HYDRA_CPU_RESET_REG 0x8003003C
30 #define HYDRA_CPU_RESET_DATA 0x00000400
32 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
33 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
35 #define HYDRA_RESET_BBAND_REG 0x80030024
36 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml81 "^usb3-phy@[0-9a-f]+$":
109 const: 0
112 const: 0
121 "^dp-phy@[0-9a-f]+$":
139 const: 0
167 reg = <0x088e9000 0x18c>,
168 <0x088e8000 0x10>,
169 <0x088ea000 0x40>;
174 ranges = <0x0 0x088e9000 0x2000>;
190 reg = <0x200 0x128>,
[all …]
/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/linux-5.10/arch/c6x/platforms/
Dcache.c16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
[all …]
/linux-5.10/drivers/clk/imx/
Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
406 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
411 base = of_iomap(np, 0); in imx7d_clocks_init()
415 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
416 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
417 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
418 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
419 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
420 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
Dclk-imx8mm.c317 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
326 base = of_iomap(np, 0); in imx8mm_clocks_probe()
331 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
332 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
333 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
334 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
335 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
336 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
337 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
338 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
Dclk-imx8mp.c433 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
439 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
454 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
462 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
463 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
464 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
465 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
466 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
467 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
468 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
Dclk-imx8mq.c299 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
309 base = of_iomap(np, 0); in imx8mq_clocks_probe()
314 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
315 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
316 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
317 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
318 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
319 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
320 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
321 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43legacy/
Dilt.c23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
/linux-5.10/drivers/media/usb/dvb-usb/
Daf9005.c26 module_param_named(dump_eeprom, dvb_usb_af9005_dump_eeprom, int, 0);
37 u8 regmask[8] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
62 st->data[0] = 14; /* rest of buffer length low */ in af9005_generic_read_write()
63 st->data[1] = 0; /* rest of buffer length high */ in af9005_generic_read_write()
71 st->data[6] = (u8) (reg & 0xff); in af9005_generic_read_write()
84 for (i = 0; i < len; i++) in af9005_generic_read_write()
88 st->data[8] = values[0]; in af9005_generic_read_write()
91 ret = dvb_usb_generic_rw(d, st->data, 16, st->data, 17, 0); in af9005_generic_read_write()
101 if (st->data[3] != 0x0d) { in af9005_generic_read_write()
118 if (st->data[16] != 0x01) { in af9005_generic_read_write()
[all …]
Daf9005.h18 #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
19 #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
20 #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
21 #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
22 #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
23 #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args)
36 #define AF9005_OFDM_REG 0
39 #define AF9005_REGISTER_RW 0x20
40 #define AF9005_REGISTER_RW_ACK 0x21
42 #define AF9005_CMD_OFDM_REG 0x00
[all …]
/linux-5.10/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux-5.10/Documentation/networking/device_drivers/ethernet/3com/
Dvortex.rst91 Where N is a number from 0 to 7. Anything above 3 produces a lot
98 them with option 0x204 you would use::
100 options=0x204,0x204
108 0 10baseT
125 0x8000 Set driver debugging level to 7
126 0x4000 Set driver debugging level to 2
127 0x0400 Enable Wake-on-LAN
128 0x0200 Force full duplex mode.
129 0x0010 Bus-master enable bit (Old Vortex cards only)
134 insmod 3c59x options=0x204
[all …]
/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43/
Dtables.c21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
/linux-5.10/sound/pci/vx222/
Dvx222_ops.c23 [VX_ICR] = 0x00,
24 [VX_CVR] = 0x04,
25 [VX_ISR] = 0x08,
26 [VX_IVR] = 0x0c,
27 [VX_RXH] = 0x14,
28 [VX_RXM] = 0x18,
29 [VX_RXL] = 0x1c,
30 [VX_DMA] = 0x10,
31 [VX_CDSP] = 0x20,
32 [VX_CFG] = 0x24,
[all …]
/linux-5.10/arch/arm/boot/dts/
Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
81 #clock-cells = <0>;
[all …]
/linux-5.10/include/linux/
Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux-5.10/drivers/usb/storage/
Dunusual_devs.h56 UNUSUAL_DEV( 0x03eb, 0x2002, 0x0100, 0x0100,
63 UNUSUAL_DEV( 0x03ee, 0x6906, 0x0003, 0x0003,
69 UNUSUAL_DEV( 0x03f0, 0x0107, 0x0200, 0x0200,
72 USB_SC_8070, USB_PR_CB, NULL, 0),
75 UNUSUAL_DEV( 0x03f0, 0x070c, 0x0000, 0x0000,
85 UNUSUAL_DEV( 0x03f0, 0x4002, 0x0001, 0x0001,
90 UNUSUAL_DEV( 0x03f3, 0x0001, 0x0000, 0x9999,
101 UNUSUAL_DEV( 0x0409, 0x0040, 0x0000, 0x9999,
108 UNUSUAL_DEV( 0x040d, 0x6205, 0x0003, 0x0003,
119 UNUSUAL_DEV( 0x0411, 0x001c, 0x0113, 0x0113,
[all …]
/linux-5.10/drivers/gpu/drm/radeon/
Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/
Dcudbg_lib.c19 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
20 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
21 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
22 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
23 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
24 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
25 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
26 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
27 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
28 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
[all …]
/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]

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