Lines Matching +full:0 +full:xa400

37 	CONTEXT_REG_BASE = 0xA000,
38 	CONTEXT_REG_END = 0xA400,
44 	USERCONFIG_REG_BASE = 0xC000,
45 	USERCONFIG_REG_END = 0x10000,
51 	AMD_CONFIG_REG_BASE = 0x2000,	/* in dwords */
52 	AMD_CONFIG_REG_END = 0x2B00,
58 	SH_REG_BASE = 0x2C00,
59 	SH_REG_END = 0x3000,
64 #define SQ_CMD						0x8DEC
67 	SQ_IND_CMD_CMD_NULL = 0x00000000,
68 	SQ_IND_CMD_CMD_HALT = 0x00000001,
69 	SQ_IND_CMD_CMD_RESUME = 0x00000002,
70 	SQ_IND_CMD_CMD_KILL = 0x00000003,
71 	SQ_IND_CMD_CMD_DEBUG = 0x00000004,
72 	SQ_IND_CMD_CMD_TRAP = 0x00000005,
76 	SQ_IND_CMD_MODE_SINGLE = 0x00000000,
77 	SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
78 	SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
79 	SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
80 	SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
175 	QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */
210 	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
211 	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
212 	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
215 	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
224 	ADDRESS_WATCH_REG_ADDR_HI = 0,