Searched +full:0 +full:x875 (Results 1 – 9 of 9) sorted by relevance
139 const: 0148 "^ethernet-phy@[0-9a-f]$":191 reg = <0xfffc4000 0x4000>;193 cdns,rx-watermark = <0x44>;195 local-mac-address = [3a 0e 03 04 05 06];199 #size-cells = <0>;202 reg = <0x1>;218 interrupts = <0 59 4>, <0 5[all...]
27 #define mmMC_CONFIG 0x80028 #define mmMC_ARB_AGE_CNTL 0x9bf29 #define mmMC_ARB_RET_CREDITS2 0x9c030 #define mmMC_ARB_FED_CNTL 0x9c131 #define mmMC_ARB_GECC2_STATUS 0x9c232 #define mmMC_ARB_GECC2_MISC 0x9c333 #define mmMC_ARB_GECC2_DEBUG 0x9c434 #define mmMC_ARB_GECC2_DEBUG2 0x9c535 #define mmMC_ARB_GECC2 0x9c936 #define mmMC_ARB_GECC2_CLI 0x9c[all...]
27 #define mmMC_CONFIG 0x80028 #define mmMC_ARB_ATOMIC 0x9be29 #define mmMC_ARB_AGE_CNTL 0x9bf30 #define mmMC_ARB_RET_CREDITS2 0x9c031 #define mmMC_ARB_FED_CNTL 0x9c132 #define mmMC_ARB_GECC2_STATUS 0x9c233 #define mmMC_ARB_GECC2_MISC 0x9c334 #define mmMC_ARB_GECC2_DEBUG 0x9c435 #define mmMC_ARB_GECC2_DEBUG2 0x9c536 #define mmMC_ARB_PERF_CID 0x9c[all...]
27 #define mmMC_CONFIG 0x80028 #define mmMC_ARB_AGE_CNTL 0x9bf29 #define mmMC_ARB_RET_CREDITS2 0x9c030 #define mmMC_ARB_FED_CNTL 0x9c131 #define mmMC_ARB_GECC2_STATUS 0x9c232 #define mmMC_ARB_GECC2_MISC 0x9c333 #define mmMC_ARB_GECC2_DEBUG 0x9c434 #define mmMC_ARB_GECC2_DEBUG2 0x9c535 #define mmMC_ARB_PERF_CID 0x9c636 #define mmMC_ARB_GECC2 0x9c[all...]
24 #define RJ54N1_DEV_CODE 0x040025 #define RJ54N1_DEV_CODE2 0x040126 #define RJ54N1_OUT_SEL 0x040327 #define RJ54N1_XY_OUTPUT_SIZE_S_H 0x040428 #define RJ54N1_X_OUTPUT_SIZE_S_L 0x040529 #define RJ54N1_Y_OUTPUT_SIZE_S_L 0x040630 #define RJ54N1_XY_OUTPUT_SIZE_P_H 0x040731 #define RJ54N1_X_OUTPUT_SIZE_P_L 0x040832 #define RJ54N1_Y_OUTPUT_SIZE_P_L 0x040933 #define RJ54N1_LINE_LENGTH_PCK_S_H 0x040[all...]
31 bootscr-address = /bits/ 64 <0x20000000>;37 #size-cells = <0>;39 cpu0: cpu@0 {45 reg = <0x0>;55 reg = <0x1>;66 reg = <0x2>;77 reg = <0x3>;92 CPU_SLEEP_0: cpu-sleep-0 {94 arm,psci-suspend-param = <0x40000000>;135 reg = <0x[all...]
17 #define RTW8852BT_RXDCK_VER 0x118 #define RTW8852BT_IQK_VER 0x2a21 #define RTW8852BT_DPK_VER 0x0625 #define DPK_TXAGC_LOWER 0x2e26 #define DPK_TXAGC_UPPER 0x3f27 #define DPK_TXAGC_INVAL 0xff28 #define RFREG_MASKRXBB 0x003e029 #define RFREG_MASKMODE 0xf000032 RF_SHUT_DOWN = 0x0,33 RF_STANDBY = 0x[all...]
17 #define RTW8852B_RXDCK_VER 0x118 #define RTW8852B_IQK_VER 0x2a23 #define RTW8852B_DPK_VER 0x0d29 #define DPK_TXAGC_LOWER 0x2e30 #define DPK_TXAGC_UPPER 0x3f31 #define DPK_TXAGC_INVAL 0xff32 #define RFREG_MASKRXBB 0x003e033 #define RFREG_MASKMODE 0xf000036 LBK_RXIQK = 0x06,37 SYNC = 0x1[all...]