Searched +full:0 +full:x838 (Results 1 – 4 of 4) sorted by relevance
19 #define PBCQ_NEST_IRSN_COMPARE 0x1a20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)21 #define PBCQ_NEST_IRSN_MASK 0x1b22 #define PBCQ_NEST_LSI_SRC_ID 0x1f23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)24 #define PBCQ_NEST_REGS_COUNT 0x4625 #define PBCQ_NEST_MMIO_BAR0 0x4026 #define PBCQ_NEST_MMIO_BAR1 0x4127 #define PBCQ_NEST_PHB_BAR 0x4228 #define PBCQ_NEST_MMIO_MASK0 0x43[all …]
31 * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS38 #define XIVE_TRIGGER_END PPC_BIT(0)44 #define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf)45 #define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff)55 * defined on the 6 LSBs (offset below 0x40)56 * In between, we can add a cache line index from 0...3 (ie, 0, 0x80,57 * 0x100, 0x180) to select a specific snooper. Those 'snoop port61 #define TM_ADDRESS_MASK 0xC3F62 #define TM_SPECIAL_OP 0x80063 #define TM_RING_OFFSET 0x30[all …]
22 #define MV64340_CS_0_BASE_ADDR 0x00823 #define MV64340_CS_0_SIZE 0x01024 #define MV64340_CS_1_BASE_ADDR 0x20825 #define MV64340_CS_1_SIZE 0x21026 #define MV64340_CS_2_BASE_ADDR 0x01827 #define MV64340_CS_2_SIZE 0x02028 #define MV64340_CS_3_BASE_ADDR 0x21829 #define MV64340_CS_3_SIZE 0x22033 #define MV64340_DEV_CS0_BASE_ADDR 0x02834 #define MV64340_DEV_CS0_SIZE 0x030[all …]
42 #define GT_REGS (0x1000 >> 2)45 #define GT_CPU (0x000 >> 2)46 #define GT_MULTI (0x120 >> 2)48 REG32(GT_CPU, 0x000)52 #define GT_SCS10LD (0x008 >> 2)53 #define GT_SCS10HD (0x010 >> 2)54 #define GT_SCS32LD (0x018 >> 2)55 #define GT_SCS32HD (0x020 >> 2)56 #define GT_CS20LD (0x028 >> 2)57 #define GT_CS20HD (0x030 >> 2)[all …]