Lines Matching +full:0 +full:x838
42 #define GT_REGS (0x1000 >> 2)
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
48 REG32(GT_CPU, 0x000)
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
58 #define GT_CS3BOOTLD (0x038 >> 2)
59 #define GT_CS3BOOTHD (0x040 >> 2)
60 #define GT_PCI0IOLD (0x048 >> 2)
61 #define GT_PCI0IOHD (0x050 >> 2)
62 #define GT_PCI0M0LD (0x058 >> 2)
63 #define GT_PCI0M0HD (0x060 >> 2)
64 #define GT_PCI0M1LD (0x080 >> 2)
65 #define GT_PCI0M1HD (0x088 >> 2)
66 #define GT_PCI1IOLD (0x090 >> 2)
67 #define GT_PCI1IOHD (0x098 >> 2)
68 #define GT_PCI1M0LD (0x0a0 >> 2)
69 #define GT_PCI1M0HD (0x0a8 >> 2)
70 #define GT_PCI1M1LD (0x0b0 >> 2)
71 #define GT_PCI1M1HD (0x0b8 >> 2)
72 #define GT_ISD (0x068 >> 2)
74 #define GT_SCS10AR (0x0d0 >> 2)
75 #define GT_SCS32AR (0x0d8 >> 2)
76 #define GT_CS20R (0x0e0 >> 2)
77 #define GT_CS3BOOTR (0x0e8 >> 2)
79 #define GT_PCI0IOREMAP (0x0f0 >> 2)
80 #define GT_PCI0M0REMAP (0x0f8 >> 2)
81 #define GT_PCI0M1REMAP (0x100 >> 2)
82 #define GT_PCI1IOREMAP (0x108 >> 2)
83 #define GT_PCI1M0REMAP (0x110 >> 2)
84 #define GT_PCI1M1REMAP (0x118 >> 2)
87 #define GT_CPUERR_ADDRLO (0x070 >> 2)
88 #define GT_CPUERR_ADDRHI (0x078 >> 2)
89 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
90 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
91 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
94 #define GT_PCI0SYNC (0x0c0 >> 2)
95 #define GT_PCI1SYNC (0x0c8 >> 2)
98 #define GT_SCS0LD (0x400 >> 2)
99 #define GT_SCS0HD (0x404 >> 2)
100 #define GT_SCS1LD (0x408 >> 2)
101 #define GT_SCS1HD (0x40c >> 2)
102 #define GT_SCS2LD (0x410 >> 2)
103 #define GT_SCS2HD (0x414 >> 2)
104 #define GT_SCS3LD (0x418 >> 2)
105 #define GT_SCS3HD (0x41c >> 2)
106 #define GT_CS0LD (0x420 >> 2)
107 #define GT_CS0HD (0x424 >> 2)
108 #define GT_CS1LD (0x428 >> 2)
109 #define GT_CS1HD (0x42c >> 2)
110 #define GT_CS2LD (0x430 >> 2)
111 #define GT_CS2HD (0x434 >> 2)
112 #define GT_CS3LD (0x438 >> 2)
113 #define GT_CS3HD (0x43c >> 2)
114 #define GT_BOOTLD (0x440 >> 2)
115 #define GT_BOOTHD (0x444 >> 2)
116 #define GT_ADERR (0x470 >> 2)
119 #define GT_SDRAM_CFG (0x448 >> 2)
120 #define GT_SDRAM_OPMODE (0x474 >> 2)
121 #define GT_SDRAM_BM (0x478 >> 2)
122 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
125 #define GT_SDRAM_B0 (0x44c >> 2)
126 #define GT_SDRAM_B1 (0x450 >> 2)
127 #define GT_SDRAM_B2 (0x454 >> 2)
128 #define GT_SDRAM_B3 (0x458 >> 2)
131 #define GT_DEV_B0 (0x45c >> 2)
132 #define GT_DEV_B1 (0x460 >> 2)
133 #define GT_DEV_B2 (0x464 >> 2)
134 #define GT_DEV_B3 (0x468 >> 2)
135 #define GT_DEV_BOOT (0x46c >> 2)
138 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
139 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
140 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
141 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
142 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
145 #define GT_DMA0_CNT (0x800 >> 2)
146 #define GT_DMA1_CNT (0x804 >> 2)
147 #define GT_DMA2_CNT (0x808 >> 2)
148 #define GT_DMA3_CNT (0x80c >> 2)
149 #define GT_DMA0_SA (0x810 >> 2)
150 #define GT_DMA1_SA (0x814 >> 2)
151 #define GT_DMA2_SA (0x818 >> 2)
152 #define GT_DMA3_SA (0x81c >> 2)
153 #define GT_DMA0_DA (0x820 >> 2)
154 #define GT_DMA1_DA (0x824 >> 2)
155 #define GT_DMA2_DA (0x828 >> 2)
156 #define GT_DMA3_DA (0x82c >> 2)
157 #define GT_DMA0_NEXT (0x830 >> 2)
158 #define GT_DMA1_NEXT (0x834 >> 2)
159 #define GT_DMA2_NEXT (0x838 >> 2)
160 #define GT_DMA3_NEXT (0x83c >> 2)
161 #define GT_DMA0_CUR (0x870 >> 2)
162 #define GT_DMA1_CUR (0x874 >> 2)
163 #define GT_DMA2_CUR (0x878 >> 2)
164 #define GT_DMA3_CUR (0x87c >> 2)
167 #define GT_DMA0_CTRL (0x840 >> 2)
168 #define GT_DMA1_CTRL (0x844 >> 2)
169 #define GT_DMA2_CTRL (0x848 >> 2)
170 #define GT_DMA3_CTRL (0x84c >> 2)
173 #define GT_DMA_ARB (0x860 >> 2)
176 #define GT_TC0 (0x850 >> 2)
177 #define GT_TC1 (0x854 >> 2)
178 #define GT_TC2 (0x858 >> 2)
179 #define GT_TC3 (0x85c >> 2)
180 #define GT_TC_CONTROL (0x864 >> 2)
183 #define GT_PCI0_CMD (0xc00 >> 2)
184 #define GT_PCI0_TOR (0xc04 >> 2)
185 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
186 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
187 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
188 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
189 #define GT_PCI1_IACK (0xc30 >> 2)
190 #define GT_PCI0_IACK (0xc34 >> 2)
191 #define GT_PCI0_BARE (0xc3c >> 2)
192 #define GT_PCI0_PREFMBR (0xc40 >> 2)
193 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
194 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
195 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
196 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
197 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
198 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
199 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
200 #define GT_PCI1_CMD (0xc80 >> 2)
201 #define GT_PCI1_TOR (0xc84 >> 2)
202 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
203 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
204 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
205 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
206 #define GT_PCI1_BARE (0xcbc >> 2)
207 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
208 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
209 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
210 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
211 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
212 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
213 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
214 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
215 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
216 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
217 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
218 #define GT_PCI0_CFGDATA (0xcfc >> 2)
220 REG32(GT_PCI0_CMD, 0xc00)
221 FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
225 REG32(GT_PCI1_CMD, 0xc80)
226 FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
232 #define GT_INTRCAUSE (0xc18 >> 2)
233 #define GT_INTRMASK (0xc1c >> 2)
234 #define GT_PCI0_ICMASK (0xc24 >> 2)
235 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
236 #define GT_CPU_INTSEL (0xc70 >> 2)
237 #define GT_PCI0_INTSEL (0xc74 >> 2)
238 #define GT_HINTRCAUSE (0xc98 >> 2)
239 #define GT_HINTRMASK (0xc9c >> 2)
240 #define GT_PCI0_HICMASK (0xca4 >> 2)
241 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
269 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
270 * 0x1fc00000 - 0x1fd00000
277 if (end >= 0x1e000000LL && end < 0x1f100000LL) { in check_reserved_space()
278 end = 0x1e000000LL; in check_reserved_space()
280 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { in check_reserved_space()
281 begin = 0x1f100000LL; in check_reserved_space()
283 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { in check_reserved_space()
284 end = 0x1fc00000LL; in check_reserved_space()
286 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { in check_reserved_space()
287 begin = 0x1fd00000LL; in check_reserved_space()
290 if (end >= 0x1f100000LL && begin < 0x1e000000LL) { in check_reserved_space()
291 end = 0x1e000000LL; in check_reserved_space()
293 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { in check_reserved_space()
294 end = 0x1fc00000LL; in check_reserved_space()
303 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ in gt64120_isd_mapping()
304 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; in gt64120_isd_mapping()
305 hwaddr length = 0x1000; in gt64120_isd_mapping()
313 length = 0x1000; in gt64120_isd_mapping()
328 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { in gt64120_pci_mapping()
337 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; in gt64120_pci_mapping()
340 get_system_io(), 0, s->PCI0IO_length); in gt64120_pci_mapping()
347 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { in gt64120_pci_mapping()
356 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; in gt64120_pci_mapping()
367 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { in gt64120_pci_mapping()
376 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; in gt64120_pci_mapping()
396 return 0; in gt64120_post_load()
417 if (!(s->regs[GT_CPU] & 0x00001000)) { in gt64120_writel()
433 s->regs[GT_PCI0IOLD] = val & 0x00007fff; in gt64120_writel()
434 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; in gt64120_writel()
438 s->regs[GT_PCI0M0LD] = val & 0x00007fff; in gt64120_writel()
439 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; in gt64120_writel()
443 s->regs[GT_PCI0M1LD] = val & 0x00007fff; in gt64120_writel()
444 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; in gt64120_writel()
448 s->regs[GT_PCI1IOLD] = val & 0x00007fff; in gt64120_writel()
449 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; in gt64120_writel()
452 s->regs[GT_PCI1M0LD] = val & 0x00007fff; in gt64120_writel()
453 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; in gt64120_writel()
456 s->regs[GT_PCI1M1LD] = val & 0x00007fff; in gt64120_writel()
457 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; in gt64120_writel()
462 s->regs[saddr] = val & 0x0000007f; in gt64120_writel()
468 s->regs[saddr] = val & 0x0000007f; in gt64120_writel()
471 s->regs[saddr] = val & 0x00007fff; in gt64120_writel()
481 s->regs[saddr] = val & 0x000007ff; in gt64120_writel()
493 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
503 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
545 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
558 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
595 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
608 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
615 s->regs[saddr] = val & 0x0401fc0f; in gt64120_writel()
652 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
663 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); in gt64120_writel()
664 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); in gt64120_writel()
668 s->regs[saddr] = val & 0x3c3ffffe; in gt64120_writel()
672 s->regs[saddr] = val & 0x03fffffe; in gt64120_writel()
676 s->regs[saddr] = val & 0x0000003f; in gt64120_writel()
705 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", in gt64120_writel()
747 val = 0xc000ffee; in gt64120_readl()
971 "reg:0x%03x size:%u value:0x%0*x\n", in gt64120_readl()
976 if (!(s->regs[GT_CPU] & 0x00001000)) { in gt64120_readl()
997 /*check for bus == 0 && device == 0, Bits 11:15 = Device , Bits 16:23 = Bus*/ in bswap()
998 bool is_phb_dev0 = extract32(phb->config_reg, 11, 13) == 0; in bswap()
1043 s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0; in gt64120_reset()
1044 s->regs[GT_MULTI] = 0x00000003; in gt64120_reset()
1047 s->regs[GT_SCS10LD] = 0x00000000; in gt64120_reset()
1048 s->regs[GT_SCS10HD] = 0x00000007; in gt64120_reset()
1049 s->regs[GT_SCS32LD] = 0x00000008; in gt64120_reset()
1050 s->regs[GT_SCS32HD] = 0x0000000f; in gt64120_reset()
1051 s->regs[GT_CS20LD] = 0x000000e0; in gt64120_reset()
1052 s->regs[GT_CS20HD] = 0x00000070; in gt64120_reset()
1053 s->regs[GT_CS3BOOTLD] = 0x000000f8; in gt64120_reset()
1054 s->regs[GT_CS3BOOTHD] = 0x0000007f; in gt64120_reset()
1056 s->regs[GT_PCI0IOLD] = 0x00000080; in gt64120_reset()
1057 s->regs[GT_PCI0IOHD] = 0x0000000f; in gt64120_reset()
1058 s->regs[GT_PCI0M0LD] = 0x00000090; in gt64120_reset()
1059 s->regs[GT_PCI0M0HD] = 0x0000001f; in gt64120_reset()
1060 s->regs[GT_ISD] = 0x000000a0; in gt64120_reset()
1061 s->regs[GT_PCI0M1LD] = 0x00000790; in gt64120_reset()
1062 s->regs[GT_PCI0M1HD] = 0x0000001f; in gt64120_reset()
1063 s->regs[GT_PCI1IOLD] = 0x00000100; in gt64120_reset()
1064 s->regs[GT_PCI1IOHD] = 0x0000000f; in gt64120_reset()
1065 s->regs[GT_PCI1M0LD] = 0x00000110; in gt64120_reset()
1066 s->regs[GT_PCI1M0HD] = 0x0000001f; in gt64120_reset()
1067 s->regs[GT_PCI1M1LD] = 0x00000120; in gt64120_reset()
1068 s->regs[GT_PCI1M1HD] = 0x0000002f; in gt64120_reset()
1070 s->regs[GT_SCS10AR] = 0x00000000; in gt64120_reset()
1071 s->regs[GT_SCS32AR] = 0x00000008; in gt64120_reset()
1072 s->regs[GT_CS20R] = 0x000000e0; in gt64120_reset()
1073 s->regs[GT_CS3BOOTR] = 0x000000f8; in gt64120_reset()
1075 s->regs[GT_PCI0IOREMAP] = 0x00000080; in gt64120_reset()
1076 s->regs[GT_PCI0M0REMAP] = 0x00000090; in gt64120_reset()
1077 s->regs[GT_PCI0M1REMAP] = 0x00000790; in gt64120_reset()
1078 s->regs[GT_PCI1IOREMAP] = 0x00000100; in gt64120_reset()
1079 s->regs[GT_PCI1M0REMAP] = 0x00000110; in gt64120_reset()
1080 s->regs[GT_PCI1M1REMAP] = 0x00000120; in gt64120_reset()
1083 s->regs[GT_CPUERR_ADDRLO] = 0x00000000; in gt64120_reset()
1084 s->regs[GT_CPUERR_ADDRHI] = 0x00000000; in gt64120_reset()
1085 s->regs[GT_CPUERR_DATALO] = 0xffffffff; in gt64120_reset()
1086 s->regs[GT_CPUERR_DATAHI] = 0xffffffff; in gt64120_reset()
1087 s->regs[GT_CPUERR_PARITY] = 0x000000ff; in gt64120_reset()
1090 s->regs[GT_PCI0SYNC] = 0x00000000; in gt64120_reset()
1091 s->regs[GT_PCI1SYNC] = 0x00000000; in gt64120_reset()
1094 s->regs[GT_SCS0LD] = 0x00000000; in gt64120_reset()
1095 s->regs[GT_SCS0HD] = 0x00000007; in gt64120_reset()
1096 s->regs[GT_SCS1LD] = 0x00000008; in gt64120_reset()
1097 s->regs[GT_SCS1HD] = 0x0000000f; in gt64120_reset()
1098 s->regs[GT_SCS2LD] = 0x00000010; in gt64120_reset()
1099 s->regs[GT_SCS2HD] = 0x00000017; in gt64120_reset()
1100 s->regs[GT_SCS3LD] = 0x00000018; in gt64120_reset()
1101 s->regs[GT_SCS3HD] = 0x0000001f; in gt64120_reset()
1102 s->regs[GT_CS0LD] = 0x000000c0; in gt64120_reset()
1103 s->regs[GT_CS0HD] = 0x000000c7; in gt64120_reset()
1104 s->regs[GT_CS1LD] = 0x000000c8; in gt64120_reset()
1105 s->regs[GT_CS1HD] = 0x000000cf; in gt64120_reset()
1106 s->regs[GT_CS2LD] = 0x000000d0; in gt64120_reset()
1107 s->regs[GT_CS2HD] = 0x000000df; in gt64120_reset()
1108 s->regs[GT_CS3LD] = 0x000000f0; in gt64120_reset()
1109 s->regs[GT_CS3HD] = 0x000000fb; in gt64120_reset()
1110 s->regs[GT_BOOTLD] = 0x000000fc; in gt64120_reset()
1111 s->regs[GT_BOOTHD] = 0x000000ff; in gt64120_reset()
1112 s->regs[GT_ADERR] = 0xffffffff; in gt64120_reset()
1115 s->regs[GT_SDRAM_CFG] = 0x00000200; in gt64120_reset()
1116 s->regs[GT_SDRAM_OPMODE] = 0x00000000; in gt64120_reset()
1117 s->regs[GT_SDRAM_BM] = 0x00000007; in gt64120_reset()
1118 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; in gt64120_reset()
1121 s->regs[GT_SDRAM_B0] = 0x00000005; in gt64120_reset()
1122 s->regs[GT_SDRAM_B1] = 0x00000005; in gt64120_reset()
1123 s->regs[GT_SDRAM_B2] = 0x00000005; in gt64120_reset()
1124 s->regs[GT_SDRAM_B3] = 0x00000005; in gt64120_reset()
1127 s->regs[GT_ECC_ERRDATALO] = 0x00000000; in gt64120_reset()
1128 s->regs[GT_ECC_ERRDATAHI] = 0x00000000; in gt64120_reset()
1129 s->regs[GT_ECC_MEM] = 0x00000000; in gt64120_reset()
1130 s->regs[GT_ECC_CALC] = 0x00000000; in gt64120_reset()
1131 s->regs[GT_ECC_ERRADDR] = 0x00000000; in gt64120_reset()
1134 s->regs[GT_DEV_B0] = 0x386fffff; in gt64120_reset()
1135 s->regs[GT_DEV_B1] = 0x386fffff; in gt64120_reset()
1136 s->regs[GT_DEV_B2] = 0x386fffff; in gt64120_reset()
1137 s->regs[GT_DEV_B3] = 0x386fffff; in gt64120_reset()
1138 s->regs[GT_DEV_BOOT] = 0x146fffff; in gt64120_reset()
1143 s->regs[GT_TC0] = 0xffffffff; in gt64120_reset()
1144 s->regs[GT_TC1] = 0x00ffffff; in gt64120_reset()
1145 s->regs[GT_TC2] = 0x00ffffff; in gt64120_reset()
1146 s->regs[GT_TC3] = 0x00ffffff; in gt64120_reset()
1147 s->regs[GT_TC_CONTROL] = 0x00000000; in gt64120_reset()
1150 s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0; in gt64120_reset()
1151 s->regs[GT_PCI0_TOR] = 0x0000070f; in gt64120_reset()
1152 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; in gt64120_reset()
1153 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; in gt64120_reset()
1154 s->regs[GT_PCI0_BS_CS20] = 0x01fff000; in gt64120_reset()
1155 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; in gt64120_reset()
1156 s->regs[GT_PCI1_IACK] = 0x00000000; in gt64120_reset()
1157 s->regs[GT_PCI0_IACK] = 0x00000000; in gt64120_reset()
1158 s->regs[GT_PCI0_BARE] = 0x0000000f; in gt64120_reset()
1159 s->regs[GT_PCI0_PREFMBR] = 0x00000040; in gt64120_reset()
1160 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; in gt64120_reset()
1161 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; in gt64120_reset()
1162 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; in gt64120_reset()
1163 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; in gt64120_reset()
1164 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; in gt64120_reset()
1165 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; in gt64120_reset()
1166 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; in gt64120_reset()
1167 s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0; in gt64120_reset()
1168 s->regs[GT_PCI1_TOR] = 0x0000070f; in gt64120_reset()
1169 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; in gt64120_reset()
1170 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; in gt64120_reset()
1171 s->regs[GT_PCI1_BS_CS20] = 0x01fff000; in gt64120_reset()
1172 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; in gt64120_reset()
1173 s->regs[GT_PCI1_BARE] = 0x0000000f; in gt64120_reset()
1174 s->regs[GT_PCI1_PREFMBR] = 0x00000040; in gt64120_reset()
1175 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; in gt64120_reset()
1176 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; in gt64120_reset()
1177 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; in gt64120_reset()
1178 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; in gt64120_reset()
1179 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; in gt64120_reset()
1180 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; in gt64120_reset()
1181 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; in gt64120_reset()
1182 s->regs[GT_PCI1_CFGADDR] = 0x00000000; in gt64120_reset()
1183 s->regs[GT_PCI1_CFGDATA] = 0x00000000; in gt64120_reset()
1184 s->regs[GT_PCI0_CFGADDR] = 0x00000000; in gt64120_reset()
1198 "gt64120-isd", 0x1000); in gt64120_realize()
1204 PCI_DEVFN(18, 0), TYPE_PCI_BUS); in gt64120_realize()
1206 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); in gt64120_realize()
1225 empty_slot_init("GT64120", 0, 0x20000000); in gt64120_realize()
1232 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ in gt64120_pci_realize()
1233 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ in gt64120_pci_realize()
1234 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ in gt64120_pci_realize()
1235 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ in gt64120_pci_realize()
1236 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ in gt64120_pci_realize()
1237 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ in gt64120_pci_realize()
1246 pci_set_word(d->config + PCI_COMMAND, 0); in gt64120_pci_reset_hold()
1249 pci_config_set_prog_interface(d->config, 0); in gt64120_pci_reset_hold()
1251 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); in gt64120_pci_reset_hold()
1252 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); in gt64120_pci_reset_hold()
1253 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); in gt64120_pci_reset_hold()
1254 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); in gt64120_pci_reset_hold()
1255 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); in gt64120_pci_reset_hold()
1256 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); in gt64120_pci_reset_hold()
1258 pci_set_byte(d->config + 0x3d, 0x01); in gt64120_pci_reset_hold()
1271 k->revision = 0x10; in gt64120_pci_class_init()