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/linux/include/uapi/linux/
H A Dtimex.h139 #define ADJ_OFFSET 0x0001 /* time offset */
140 #define ADJ_FREQUENCY 0x0002 /* frequency offset */
141 #define ADJ_MAXERROR 0x0004 /* maximum time error */
142 #define ADJ_ESTERROR 0x0008 /* estimated time error */
143 #define ADJ_STATUS 0x0010 /* clock status */
144 #define ADJ_TIMECONST 0x0020 /* pll time constant */
145 #define ADJ_TAI 0x0080 /* set TAI offset */
146 #define ADJ_SETOFFSET 0x0100 /* add 'time' to current time */
147 #define ADJ_MICRO 0x1000 /* select microsecond resolution */
148 #define ADJ_NANO 0x200
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/linux/arch/x86/um/
H A Dptrace.c20 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ in twd_i387_to_fxsr()
22 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ in twd_i387_to_fxsr()
23 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ in twd_i387_to_fxsr()
24 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ in twd_i387_to_fxsr()
34 unsigned long ret = 0xffff0000; in twd_fxsr_to_i387()
39 for (i = 0; i < 8; i++) { in twd_fxsr_to_i387()
40 if (twd & 0x1) { in twd_fxsr_to_i387()
43 switch (st->exponent & 0x7fff) { in twd_fxsr_to_i387()
44 case 0x7ff in twd_fxsr_to_i387()
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/linux/include/scsi/fc/
H A Dfc_fip.h17 #define FIP_DEF_FC_MAP 0x0efc00 /* default FCoE MAP (MAC OUI) value */
25 #define FIP_VN_FC_MAP 0x0efd00 /* MAC OUI for VN2VN use */
36 #define FIP_ALL_FCOE_MACS ((__u8[6]) { 1, 0x10, 0x18, 1, 0, 0 })
37 #define FIP_ALL_ENODE_MACS ((__u8[6]) { 1, 0x10, 0x18, 1, 0, 1 })
38 #define FIP_ALL_FCF_MACS ((__u8[6]) { 1, 0x1
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/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c61 xlb = of_iomap(np, 0); in mpc5200_setup_xlb_arbiter()
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
144 mpc52xx_wdt = of_iomap(np, 0); in mpc52xx_map_common_devices()
152 mpc52xx_cdm = of_iomap(np, 0); in mpc52xx_map_common_devices()
157 simple_gpio = of_iomap(np, 0); in mpc52xx_map_common_devices()
162 wkup_gpio = of_iomap(np, 0); in mpc52xx_map_common_devices()
183 mclken_div = 0x8000 | (clkdiv & 0x1F in mpc52xx_set_psc_clkdiv()
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/linux/drivers/pci/controller/dwc/
H A Dpcie-armada8k.c37 #define PCIE_VENDOR_REGS_OFFSET 0x8000
39 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
42 #define PCIE_DEVICE_TYPE_MASK 0xF
43 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
45 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
49 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
50 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
56 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
57 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x5
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/linux/drivers/media/test-drivers/vivid/
H A Dvivid-radio-rx.c39 return 0; in vivid_radio_rx_read()
59 if (dev->radio_rx_rds_last_block == 0 || in vivid_radio_rx_read()
87 /* abs(dev->radio_rx_sig_qual) <= 200, map that to a 0-50% range */ in vivid_radio_rx_read()
90 for (i = 0; i < size && blk > dev->radio_rx_rds_last_block; in vivid_radio_rx_read()
95 if (data_blk == 0 && dev->radio_rds_loop) in vivid_radio_rx_read()
99 case 0: in vivid_radio_rx_read()
138 if (band->tuner != 0) in vivid_radio_rx_enum_freq_bands()
145 return 0; in vivid_radio_rx_enum_freq_bands()
170 for (band = 0; band < TOT_BANDS; band++) in vivid_radio_rx_s_hw_freq_seek()
183 for (band = 0; ban in vivid_radio_rx_s_hw_freq_seek()
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/linux/drivers/media/i2c/
H A Dtda1997x_regs.h6 /* Page 0x00 - General Control */
7 #define REG_VERSION 0x0000
8 #define REG_INPUT_SEL 0x0001
9 #define REG_SVC_MODE 0x0002
10 #define REG_HPD_MAN_CTRL 0x0003
11 #define REG_RT_MAN_CTRL 0x0004
12 #define REG_STANDBY_SOFT_RST 0x000A
13 #define REG_HDMI_SOFT_RST 0x000B
14 #define REG_HDMI_INFO_RST 0x000C
15 #define REG_INT_FLG_CLR_TOP 0x000
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H A Dmt9m001.c24 * mt9m001 i2c address 0x5d
28 #define MT9M001_CHIP_VERSION 0x00
29 #define MT9M001_ROW_START 0x01
30 #define MT9M001_COLUMN_START 0x02
31 #define MT9M001_WINDOW_HEIGHT 0x03
32 #define MT9M001_WINDOW_WIDTH 0x04
33 #define MT9M001_HORIZONTAL_BLANKING 0x05
34 #define MT9M001_VERTICAL_BLANKING 0x06
35 #define MT9M001_OUTPUT_CONTROL 0x07
36 #define MT9M001_SHUTTER_WIDTH 0x0
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/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_type.h16 #define FM10K_DEV_ID_PF 0x15A4
17 #define FM10K_DEV_ID_VF 0x15A5
18 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
19 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
25 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
26 #define FM10K_STAT_VALID 0x80000000
29 #define FM10K_PCIE_LINK_CAP 0x7C
30 #define FM10K_PCIE_LINK_STATUS 0x82
31 #define FM10K_PCIE_LINK_WIDTH 0x3F0
32 #define FM10K_PCIE_LINK_WIDTH_1 0x1
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/linux/arch/powerpc/perf/
H A Dpower6-pmu.c19 #define PM_PMC_MSK 0x7
22 #define PM_UNIT_MSK 0xf
24 #define PM_LLAV 0x8000 /* Load lookahead match value */
25 #define PM_LLA 0x4000 /* Load lookahead match enable */
31 #define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
32 #define PM_BUSEVENT_MSK 0xf3700
39 #define MMCR1_TTMSEL_MSK 0xf
42 #define MMCR1_NESTSEL_MSK 0x7
49 #define MMCR1_PMCSEL_MSK 0xf
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dwq.h170 int smaller = 0x8000 & (cc1 - cc2); in mlx5_wq_cyc_cc_bigger()
227 *wq->db = cpu_to_be32(wq->cc & 0xffffff); in mlx5_cqwq_update_db_record()
249 u8 sw_validity_iteration_count = mlx5_cqwq_get_wrap_cnt(wq) & 0xff; in mlx5_cqwq_get_cqe_enhanced_comp()
/linux/drivers/net/wwan/
H A Dmhi_wwan_ctrl.c16 #define MHI_WWAN_MAX_MTU 0x8000
126 return 0; in mhi_wwan_ctrl_start()
248 return 0; in mhi_wwan_ctrl_probe()
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x0030000
[all...]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datl1.h56 #define IDLE_STATUS_RXMAC 0x1
57 #define IDLE_STATUS_TXMAC 0x2
58 #define IDLE_STATUS_RXQ 0x4
59 #define IDLE_STATUS_TXQ 0x8
60 #define IDLE_STATUS_DMAR 0x10
61 #define IDLE_STATUS_DMAW 0x20
62 #define IDLE_STATUS_SMB 0x40
63 #define IDLE_STATUS_CMB 0x80
69 #define MAC_CTRL_TX_PAUSE 0x10000
70 #define MAC_CTRL_SCNT 0x2000
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/linux/include/linux/
H A Dpe.h14 * Starting from version v3.0, the major version field should be interpreted as
16 * - 0x1: initrd loading from the LINUX_EFI_INITRD_MEDIA_GUID device path,
17 * - 0x2: initrd loading using the initrd= command line option, where the file
21 * The recommended way of loading and starting v1.0 or later kernels is to use
25 * Versions older than v1.0 may support initrd loading via the image load
29 * The minor version field must remain 0x0.
32 #define LINUX_EFISTUB_MAJOR_VERSION 0x3
33 #define LINUX_EFISTUB_MINOR_VERSION 0x0
36 * LINUX_PE_MAGIC appears at offset 0x38 into the MS-DOS header of EFI bootable
40 #define LINUX_PE_MAGIC 0x818223c
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/linux/drivers/ssb/
H A Ddriver_pcicore.c75 u32 addr = 0; in get_cfgspace_addr()
82 if (bus == 0) { in get_cfgspace_addr()
83 /* Type 0 transaction */ in get_cfgspace_addr()
131 val = 0xffffffff; in ssb_extpci_read_config()
149 err = 0; in ssb_extpci_read_config()
162 u32 addr, val = 0; in ssb_extpci_write_config()
177 val = 0xffffffff; in ssb_extpci_write_config()
184 val &= ~(0xFF << (8 * (off & 3))); in ssb_extpci_write_config()
189 val &= ~(0xFFFF << (8 * (off & 3))); in ssb_extpci_write_config()
198 err = 0; in ssb_extpci_write_config()
[all...]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
34 reg = <0x1>;
42 reg = <0x2>;
50 reg = <0x3>;
56 cpu0_opp_table: opp-table-0 {
103 reg = <0x10080000 0x8000>;
[all...]
/linux/arch/powerpc/boot/
H A Drs6000.h66 #define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */
67 #define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */
68 #define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */
100 #define STYP_LOADER 0x1000
103 #define STYP_DEBUG 0x2000
107 #define STYP_OVRFLO 0x8000
113 * grouping will have l_lnno = 0 and in place of physical address will be the
118 char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
217 #define DBXMASK 0x8
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/linux/sound/oss/dmasound/
H A Ddmasound_atari.c32 #define DMASOUND_ATARI_REVISION 0
168 while (count > 0) { in ata_ct_law()
208 while (count > 0) { in ata_ct_u8()
212 *p++ = data ^ 0x80; in ata_ct_u8()
219 while (count > 0) { in ata_ct_u8()
224 *p++ = data ^ 0x8080; in ata_ct_u8()
243 while (count > 0) { in ata_ct_s16be()
275 while (count > 0) { in ata_ct_u16be()
280 data ^= 0x8000; in ata_ct_u16be()
[all...]
/linux/drivers/firmware/
H A Dti_sci.h16 #define TI_SCI_MSG_ENABLE_WDT 0x0000
17 #define TI_SCI_MSG_WAKE_RESET 0x0001
18 #define TI_SCI_MSG_VERSION 0x0002
19 #define TI_SCI_MSG_WAKE_REASON 0x0003
20 #define TI_SCI_MSG_GOODBYE 0x0004
21 #define TI_SCI_MSG_SYS_RESET 0x0005
22 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022
25 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
26 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
27 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x020
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/linux/arch/s390/include/asm/
H A Dkvm_host_types.h12 #define SIGP_CTRL_C 0x80
13 #define SIGP_CTRL_SCN_MASK 0x3f
108 #define SIDAD_SIZE_MASK 0xff
113 #define CPUSTAT_STOPPED 0x80000000
114 #define CPUSTAT_WAIT 0x10000000
115 #define CPUSTAT_ECALL_PEND 0x08000000
116 #define CPUSTAT_STOP_INT 0x04000000
117 #define CPUSTAT_IO_INT 0x02000000
118 #define CPUSTAT_EXT_INT 0x01000000
119 #define CPUSTAT_RUNNING 0x0080000
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/linux/arch/powerpc/boot/dts/
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x0000000
[all...]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x800
[all...]
/linux/sound/pci/ymfpci/
H A Dymfpci.h22 #define YDSXGR_INTFLAG 0x0004
23 #define YDSXGR_ACTIVITY 0x0006
24 #define YDSXGR_GLOBALCTRL 0x0008
25 #define YDSXGR_ZVCTRL 0x000A
26 #define YDSXGR_TIMERCTRL 0x0010
27 #define YDSXGR_TIMERCOUNT 0x0012
28 #define YDSXGR_SPDIFOUTCTRL 0x0018
29 #define YDSXGR_SPDIFOUTSTATUS 0x001C
30 #define YDSXGR_EEPROMCTRL 0x0020
31 #define YDSXGR_SPDIFINCTRL 0x003
[all...]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x78400
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