Lines Matching +full:0 +full:x8000
23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
97 reg = <0x1e000 0x100>;
102 reg = <0x1f000 0x1000
103 0x1e100 0x100>;
105 #address-cells = <0>;
111 reg = <0x1e200 0x20>;
118 reg = <0x1e600 0x20>;
126 reg = <0x1e620 0x20>;
132 #clock-cells = <0>;
135 reg = <0x20000 0xf00>;
140 reg = <0x4800c0 0x10>;
146 reg = <0x4800e0 0x10>;
153 reg = <0xa000 0x9ac>, <0x8040 0x24>;
156 #size-cells = <0>;
161 sata0: sata-port@0 {
162 reg = <0>;
169 reg = <0x8100 0x1e00>;
172 #size-cells = <0>;
175 sata_phy0: sata-phy@0 {
176 reg = <0>;
177 #phy-cells = <0>;
187 ranges = <0 0xfffe8000 0x10000>;
191 reg = <0x80 0x3c>;
194 /* GPIOs 0 .. 31 */
197 reg = <0x100 0x04>, <0x114 0x04>;
207 reg = <0x104 0x04>, <0x118 0x04>;
217 reg = <0x108 0x04>, <0x11c 0x04>;
227 reg = <0x10c 0x04>, <0x120 0x04>;
237 reg = <0x110 0x04>, <0x124 0x04>;
246 reg = <0x300 0x28>;
252 reg = <0x600 0x1b>;
261 reg = <0x620 0x1b>;
270 #size-cells = <0>;
272 reg = <0x700 0xdc>;
278 #size-cells = <0>;
279 compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
280 reg = <0x1000 0x600>;
290 #size-cells = <0>;
291 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
292 reg = <0x2000 0x600>, <0xf0 0x10>;
298 nandcs: nand@0 {
300 reg = <0>;
306 reg = <0x4400 0x1e0>;
312 reg = <0x8000 0x50>;
318 arm,primecell-periphid = <0x00041081>;
319 reg = <0xd000 0x1000>;
331 offset = <0x34>;