Home
last modified time | relevance | path

Searched +full:0 +full:x8000 (Results 201 – 225 of 1419) sorted by relevance

12345678910>>...57

/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
H A Dk3-am62-wakeup.dtsi14 reg = <0x00 0x43000000 0x00 0x20000>;
17 ranges = <0x0 0x00 0x43000000 0x20000>;
22 reg = <0x14 0x4>;
27 reg = <0x18 0x4>;
32 reg = <0x200 0x8>;
37 reg = <0x4008 0x4>;
42 reg = <0x4018 0x4>;
48 reg = <0x00 0x2b300050 0x00 0x4>,
49 <0x00 0x2b300054 0x00 0x4>,
50 <0x00 0x2b300058 0x00 0x4>;
[all …]
H A Dk3-am62p-j722s-common-wakeup.dtsi13 reg = <0x00 0x43000000 0x00 0x20000>;
16 ranges = <0x00 0x00 0x43000000 0x20000>;
21 reg = <0x14 0x4>;
27 reg = <0x18 0x4>;
32 reg = <0x200 0x8>;
37 reg = <0x4008 0x4>;
42 reg = <0x4018 0x4>;
48 reg = <0 0x2b300050 0 0x4>,
49 <0 0x2b300054 0 0x4>,
50 <0 0x2b300058 0 0x4>;
[all …]
H A Dk3-am62a-wakeup.dtsi15 ranges = <0x00 0x00 0x43000000 0x20000>;
19 reg = <0x14 0x4>;
25 reg = <0x18 0x4>;
30 reg = <0x200 0x8>;
35 reg = <0x4008 0x4>;
40 reg = <0x4018 0x4>;
46 reg = <0 0x2b300050 0 0x4>,
47 <0 0x2b300054 0 0x4>,
48 <0 0x2b300058 0 0x4>;
60 clocks = <&k3_clks 114 0>;
[all …]
/linux/include/uapi/linux/
H A Dif_tunnel.h12 #define SIOCGETTUNNEL (SIOCDEVPRIVATE + 0)
25 #define GRE_CSUM __cpu_to_be16(0x8000)
26 #define GRE_ROUTING __cpu_to_be16(0x4000)
27 #define GRE_KEY __cpu_to_be16(0x2000)
28 #define GRE_SEQ __cpu_to_be16(0x1000)
29 #define GRE_STRICT __cpu_to_be16(0x0800)
30 #define GRE_REC __cpu_to_be16(0x0700)
31 #define GRE_ACK __cpu_to_be16(0x0080)
32 #define GRE_FLAGS __cpu_to_be16(0x0078)
33 #define GRE_VERSION __cpu_to_be16(0x0007)
[all …]
/linux/sound/soc/codecs/
H A Drt5682.c43 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
44 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
45 {RT5682_I2C_CTRL, 0x000f},
46 {RT5682_PLL2_INTERNAL, 0x8266},
47 {RT5682_SAR_IL_CMD_1, 0x22b7},
48 {RT5682_SAR_IL_CMD_3, 0x0365},
49 {RT5682_SAR_IL_CMD_6, 0x0110},
50 {RT5682_CHARGE_PUMP_1, 0x0210},
51 {RT5682_HP_LOGIC_CTRL_2, 0x0007},
52 {RT5682_SAR_IL_CMD_2, 0xac00},
[all …]
H A Dwm8993.h15 #define WM8993_SOFTWARE_RESET 0x00
16 #define WM8993_POWER_MANAGEMENT_1 0x01
17 #define WM8993_POWER_MANAGEMENT_2 0x02
18 #define WM8993_POWER_MANAGEMENT_3 0x03
19 #define WM8993_AUDIO_INTERFACE_1 0x04
20 #define WM8993_AUDIO_INTERFACE_2 0x05
21 #define WM8993_CLOCKING_1 0x06
22 #define WM8993_CLOCKING_2 0x07
23 #define WM8993_AUDIO_INTERFACE_3 0x08
24 #define WM8993_AUDIO_INTERFACE_4 0x09
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
67 i-cache-size = <0x8000>;
70 d-cache-size = <0x8000>;
84 reg = <0x1>;
87 i-cache-size = <0x8000>;
90 d-cache-size = <0x8000>;
102 reg = <0x2>;
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c13 #define EEPROM_READ 0xc000 /* serial memory read */
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
17 #define EEPROM_WDS 0x8000 /* disable all programming */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
22 #define EEPROM_PRDS 0x8000 /* disable protect register, forever */
[all …]
/linux/drivers/staging/media/av7110/
H A Dav7110_ir.c16 #define IR_RC5 0
33 command = ircom & 0x3f; in av7110_ir_handler()
34 addr = (ircom >> 6) & 0x1f; in av7110_ir_handler()
36 toggle = ircom & 0x0800; in av7110_ir_handler()
41 scancode = ircom & ~0x8000; in av7110_ir_handler()
42 toggle = ircom & 0x8000; in av7110_ir_handler()
53 command = ircom & 0x3f; in av7110_ir_handler()
54 addr = (ircom >> 6) & 0x1f; in av7110_ir_handler()
55 if (!(ircom & 0x1000)) in av7110_ir_handler()
56 command |= 0x40; in av7110_ir_handler()
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/linux/include/linux/mfd/wm8350/
H A Daudio.h13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
H A Drtc.h16 #define WM8350_RTC_SECONDS_MINUTES 0x10
17 #define WM8350_RTC_HOURS_DAY 0x11
18 #define WM8350_RTC_DATE_MONTH 0x12
19 #define WM8350_RTC_YEAR 0x13
20 #define WM8350_ALARM_SECONDS_MINUTES 0x14
21 #define WM8350_ALARM_HOURS_DAY 0x15
22 #define WM8350_ALARM_DATE_MONTH 0x16
23 #define WM8350_RTC_TIME_CONTROL 0x17
26 * R16 (0x10) - RTC Seconds/Minutes
28 #define WM8350_RTC_MINS_MASK 0x7F00
[all …]
/linux/include/linux/mfd/wm831x/
H A Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra264.dtsi22 reg = <0x0 0x86070000 0x0 0x2000>;
28 bus@0 {
34 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
38 reg = <0x0 0x00100000 0x0 0x0f000>,
39 <0x0 0x0c140000 0x0 0x10000>;
44 reg = <0x0 0x08000000 0x0 0x140000>;
54 reg = <0x0 0x08400000 0x0 0x210000>;
88 iommus = <&smmu1 0x00000800>;
90 dma-channel-mask = <0xfffffffe>;
96 reg = <0x0 0x08800000 0x0 0xd0000>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi22 reg = <0x45000000 0x00400000>;
28 reg = <0x44000000 0x01000000>;
35 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0>;
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
[all …]
/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux/drivers/media/usb/em28xx/
H A Dem28xx-audio.c45 } while (0)
54 for (i = 0; i < dev->adev.num_urb; i++) { in em28xx_deinit_isoc_audio()
63 return 0; in em28xx_deinit_isoc_audio()
71 int period_elapsed = 0; in em28xx_audio_isocirq()
81 atomic_set(&dev->adev.stream_started, 0); in em28xx_audio_isocirq()
86 case 0: /* success */ in em28xx_audio_isocirq()
98 if (atomic_read(&dev->adev.stream_started) == 0) in em28xx_audio_isocirq()
106 for (i = 0; i < urb->number_of_packets; i++) { in em28xx_audio_isocirq()
150 urb->status = 0; in em28xx_audio_isocirq()
153 if (status < 0) in em28xx_audio_isocirq()
[all …]
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi17 #size-cells = <0>;
20 cpu0: cpu@0 {
24 reg = <0x0>;
32 i-cache-size = <0x8000>;
33 i-cache-line-size = <0x40>;
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <0x40>;
50 gpio-ranges = <&pinctrl 0 0 232>;
59 reg = <0 0x110a0000 0 0x20000>;
61 #address-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
30 i-cache-size = <0x8000>;
33 d-cache-size = <0x8000>;
46 i-cache-size = <0x8000>;
49 d-cache-size = <0x8000>;
62 i-cache-size = <0x8000>;
65 d-cache-size = <0x8000>;
78 i-cache-size = <0x8000>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux/drivers/net/ethernet/via/
H A Dvia-velocity.h30 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
32 #define REV_ID_VT6110 (0)
34 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
35 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
36 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
42 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
43 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
44 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
46 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
47 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_qmath.c23 * When both the 16bit inputs are 0x8000 then the output is saturated to
24 * 0x7fffffff.
29 if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) in qm_muls16()
30 result = 0x7fffffff; in qm_muls16()
46 if (op1 < 0 && op2 < 0 && result > 0) in qm_add32()
47 result = 0x80000000; in qm_add32()
48 else if (op1 > 0 && op2 > 0 && result < 0) in qm_add32()
49 result = 0x7fffffff; in qm_add32()
63 if (temp > (s32) 0x7fff) in qm_add16()
64 result = (s16) 0x7fff; in qm_add16()
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Deeprom.h131 /* common and choice range (0x0000 - 0x0fff) */
132 #define PDR_END 0x0000
133 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
134 #define PDR_PDA_VERSION 0x0002
135 #define PDR_NIC_SERIAL_NUMBER 0x0003
136 #define PDR_NIC_RAM_SIZE 0x0005
137 #define PDR_RFMODEM_SUP_RANGE 0x0006
138 #define PDR_PRISM_MAC_SUP_RANGE 0x0007
139 #define PDR_NIC_ID 0x0008
141 #define PDR_MAC_ADDRESS 0x0101
[all …]

12345678910>>...57