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/linux/drivers/infiniband/hw/qedr/
H A Dqedr.h66 #define QEDR_CQ_MAGIC_NUMBER (0x11223344)
124 #define QEDR_ENET_STATE_BIT (0)
181 #define QEDR_MAX_SQ_PBL (0x8000)
182 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
193 #define QEDR_MAX_RQ_PBL (0x2000)
194 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
211 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
220 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
343 } while (0)
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/linux/drivers/regulator/
H A Dwm8350-regulator.c23 #define WM8350_DCDC_MAX_VSEL 0x66
135 return 0; in wm8350_isink_enable()
175 return 0; in wm8350_isink_disable()
186 0x8000; in wm8350_isink_is_enabled()
189 0x8000; in wm8350_isink_is_enabled()
213 case 0: in wm8350_isink_enable_time()
214 return 0; in wm8350_isink_enable_time()
224 case 0 in wm8350_isink_enable_time()
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/linux/drivers/net/ethernet/amd/
H A Dpcnet32.c69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
82 { 0x300, 0x320, 0x340, 0x360, 0 };
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x0
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H A Dsunlance.c121 #define LE_CSR0 0
126 #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
128 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
129 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
130 #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
131 #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
132 #define LE_C0_MERR 0x0800 /* ME: Memory error */
133 #define LE_C0_RINT 0x040
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/linux/drivers/comedi/drivers/
H A Dcb_pcidas64.c87 #define DMA_BUFFER_SIZE 0x1000
88 #define DAC_FIFO_SIZE 0x2000
91 static const int max_counter_value = 0xffffff;
97 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
98 HW_CONFIG_REG = 0x2, /* hardware config register */
99 DAQ_SYNC_REG = 0xc,
100 DAQ_ATRIG_LOW_4020_REG = 0xc,
101 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
102 ADC_CONTROL1_REG = 0x1
[all...]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type.h13 #define IXGBE_DEV_ID_82598 0x10B6
14 #define IXGBE_DEV_ID_82598_BX 0x1508
15 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
16 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
17 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
18 #define IXGBE_DEV_ID_82598AT 0x10C8
19 #define IXGBE_DEV_ID_82598AT2 0x150B
20 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
21 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
22 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F
[all...]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA1
[all...]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq_cmd.h18 #define I40E_FW_API_VERSION_MAJOR 0x0001
19 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
20 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
27 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
31 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
33 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
38 i40e_aqc_opc_get_version = 0x0001,
39 i40e_aqc_opc_driver_version = 0x0002,
40 i40e_aqc_opc_queue_shutdown = 0x000
[all...]
/linux/sound/soc/codecs/
H A Drt5631.c39 { RT5631_SPK_OUT_VOL, 0x8888 },
40 { RT5631_HP_OUT_VOL, 0x8080 },
41 { RT5631_MONO_AXO_1_2_VOL, 0xa080 },
42 { RT5631_AUX_IN_VOL, 0x0808 },
43 { RT5631_ADC_REC_MIXER, 0xf0f0 },
44 { RT5631_VDAC_DIG_VOL, 0x0010 },
45 { RT5631_OUTMIXER_L_CTRL, 0xffc0 },
46 { RT5631_OUTMIXER_R_CTRL, 0xffc0 },
47 { RT5631_AXO1MIXER_CTRL, 0x88c0 },
48 { RT5631_AXO2MIXER_CTRL, 0x88c
[all...]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.h60 #define FALSE 0
63 #define ALL_CHANNELS '\0'
64 #define ALL_TARGETS_MASK 0xFFFF
65 #define INITIATOR_WILDCARD (~0)
66 #define SCB_LIST_NULL 0xFF00
68 #define QOUTFIFO_ENTRY_VALID 0x80
69 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
76 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
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/linux/include/uapi/linux/
H A Dcomedi.h13 #define COMEDI_MAJORVERSION 0
57 ((((aref) & 0x3) << 24) | (((rng) & 0xff) << 16) | (chan))
61 #define CR_CHAN(a) ((a) & 0xffff)
62 #define CR_RANGE(a) (((a) >> 16) & 0xff)
63 #define CR_AREF(a) (((a) >> 24) & 0x03)
65 #define CR_FLAGS_MASK 0xfc000000
66 #define CR_ALT_FILTER 0x04000000
69 #define CR_ALT_SOURCE 0x08000000
70 #define CR_EDGE 0x4000000
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/linux/sound/pci/asihpi/
H A Dhpi6000.c29 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
32 #define HPI_HIF_ERROR_MASK 0x4000
100 #define INTERRUPT_EVENT_SET 0
110 #define DSP_SPACING 0x800
112 #define CONTROL 0x0000
113 #define ADDRESS 0x0200
114 #define DATA_AUTOINC 0x0400
115 #define DATA 0x0600
155 #define H6WRITE 0
402 u16 err = 0; in subsys_create_adapter()
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/linux/drivers/scsi/bfa/
H A Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x0001410
[all...]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x0001410
[all...]
/linux/arch/powerpc/boot/dts/
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe000500
[all...]
/linux/sound/pci/lola/
H A Dlola.h17 #define LOLA_BAR0_GCAP 0x00
18 #define LOLA_BAR0_VMIN 0x02
19 #define LOLA_BAR0_VMAJ 0x03
20 #define LOLA_BAR0_OUTPAY 0x04
21 #define LOLA_BAR0_INPAY 0x06
22 #define LOLA_BAR0_GCTL 0x08
23 #define LOLA_BAR0_WAKEEN 0x0c
24 #define LOLA_BAR0_STATESTS 0x0e
25 #define LOLA_BAR0_GSTS 0x10
26 #define LOLA_BAR0_OUTSTRMPAY 0x1
[all...]
/linux/include/linux/fsl/
H A Dguts.h29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
31 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 u32 porcir; /* 0x.0020 - POR Configuration Information
41 u8 res024[0x3
[all...]
/linux/arch/arm/mach-s3c/
H A Dmach-crag6410-module.c36 .dev_id = "spi0.0", /* SPI device name */
50 [0] = {
53 .bus_num = 0,
54 .chip_select = 0,
62 [0] = {
65 .bus_num = 0,
66 .chip_select = 0,
95 { WM5100_MICDET_MICBIAS3, 0, 0 },
100 0,
[all...]
/linux/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S14 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
15 #define SS_HID 0x08 /* 3 HIDs */
16 #define SS_IABR 0x14 /* 2 IABRs */
17 #define SS_IBCR 0x1c
18 #define SS_DABR 0x20 /* 2 DABRs */
19 #define SS_DBCR 0x28
20 #define SS_SP 0x2c
21 #define SS_SR 0x30 /* 16 segment registers */
22 #define SS_R2 0x70
23 #define SS_MSR 0x7
[all...]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_10_0_sm8650.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x1000,
36 .base = 0x16000, .len = 0x1000,
40 .base = 0x17000, .len = 0x100
[all...]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
[all...]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x29
[all...]
/linux/arch/alpha/include/asm/
H A Dcore_mcpcia.h58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x05
[all...]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_v6_1.c39 #define VPE_THREAD1_UCODE_OFFSET 0x8000
41 #define regVPEC_COLLABORATE_CNTL 0x0013
42 #define regVPEC_COLLABORATE_CNTL_BASE_IDX 0
43 #define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN__SHIFT 0x0
44 #define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK 0x00000001L
46 #define regVPEC_COLLABORATE_CFG 0x0014
47 #define regVPEC_COLLABORATE_CFG_BASE_IDX 0
48 #define VPEC_COLLABORATE_CFG__MASTER_ID__SHIFT 0x0
49 #define VPEC_COLLABORATE_CFG__MASTER_EN__SHIFT 0x
[all...]
/linux/arch/mips/txx9/generic/
H A Dpci.c61 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { in txx9_pci66_check()
68 if (vid == 0xffff) in txx9_pci66_check()
72 if (cap66 < 0) in txx9_pci66_check()
80 cap66 = 0; in txx9_pci66_check()
85 return cap66 > 0; in txx9_pci66_check()
94 .mem_resource = &primary_pci_mem_res[0],
106 * mem_base, io_base: physical address. 0 for auto assignment.
120 int min_size = 0x10000; in txx9_alloc_pci_controller()
126 new->r_mem[0] in txx9_alloc_pci_controller()
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