| /qemu/tests/qemu-iotests/ |
| H A D | 197.out | 13 read 0/0 bytes at offset 0
14 0 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 2 GiB (0x80010000) bytes allocated at offset 0 bytes (0x0)
21 1023.938 MiB (0x3fff0000) bytes not allocated at offset 2 GiB (0x80010000)
22 64 KiB (0x10000) bytes allocated at offset 3 GiB (0xc0000000)
23 1023.938 MiB (0x3fff0000) bytes not allocated at offset 3 GiB (0xc0010000)
30 read 1024/1024 bytes at offset 0
32 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
39 wrote 65536/65536 bytes at offset 0
45 28 KiB (0x7000) bytes not allocated at offset 0 bytes (0x0)
[all …]
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| /qemu/include/hw/pci/ |
| H A D | pci_ids.h | 16 #define PCI_CLASS_NOT_DEFINED 0x0000
17 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
19 #define PCI_BASE_CLASS_STORAGE 0x01
20 #define PCI_CLASS_STORAGE_SCSI 0x0100
21 #define PCI_CLASS_STORAGE_IDE 0x0101
22 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
23 #define PCI_CLASS_STORAGE_IPI 0x0103
24 #define PCI_CLASS_STORAGE_RAID 0x0104
25 #define PCI_CLASS_STORAGE_ATA 0x0105
26 #define PCI_CLASS_STORAGE_SATA 0x0106
[all …]
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| /qemu/tests/unit/ |
| H A D | test-bitcnt.c | 25 { { .w8 = 0x00 }, .popct=0 },
26 { { .w8 = 0x01 }, .popct=1 },
27 { { .w8 = 0x03 }, .popct=2 },
28 { { .w8 = 0x04 }, .popct=1 },
29 { { .w8 = 0x0f }, .popct=4 },
30 { { .w8 = 0x3f }, .popct=6 },
31 { { .w8 = 0x40 }, .popct=1 },
32 { { .w8 = 0xf0 }, .popct=4 },
33 { { .w8 = 0x7f }, .popct=7 },
34 { { .w8 = 0x80 }, .popct=1 },
[all …]
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| /qemu/include/hw/ppc/ |
| H A D | mac_dbdma.h | 53 #define DBDMA_CONTROL 0x00
54 #define DBDMA_STATUS 0x01
55 #define DBDMA_CMDPTR_HI 0x02
56 #define DBDMA_CMDPTR_LO 0x03
57 #define DBDMA_INTR_SEL 0x04
58 #define DBDMA_BRANCH_SEL 0x05
59 #define DBDMA_WAIT_SEL 0x06
60 #define DBDMA_XFER_MODE 0x07
61 #define DBDMA_DATA2PTR_HI 0x08
62 #define DBDMA_DATA2PTR_LO 0x09
[all …]
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| /qemu/include/hw/s390x/ |
| H A D | ioinst.h | 31 #define SCSW_FLAGS_MASK_KEY 0xf000
32 #define SCSW_FLAGS_MASK_SCTL 0x0800
33 #define SCSW_FLAGS_MASK_ESWF 0x0400
34 #define SCSW_FLAGS_MASK_CC 0x0300
35 #define SCSW_FLAGS_MASK_FMT 0x0080
36 #define SCSW_FLAGS_MASK_PFCH 0x0040
37 #define SCSW_FLAGS_MASK_ISIC 0x0020
38 #define SCSW_FLAGS_MASK_ALCC 0x0010
39 #define SCSW_FLAGS_MASK_SSI 0x0008
40 #define SCSW_FLAGS_MASK_ZCC 0x0004
[all …]
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| /qemu/include/hw/arm/ |
| H A D | raspi_platform.h | 67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
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| /qemu/hw/m68k/ |
| H A D | next-cube.c | 38 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
40 #define DPRINTF(fmt, ...) do { } while (0)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
151 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
153 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
158 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
159 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
[all …]
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| /qemu/contrib/elf2dmp/ |
| H A D | main.c | 23 #define INITIAL_MXCSR 0x1f80
27 uint16_t offset1; /* offset bits 0..15 */
42 static const uint64_t SharedUserData = 0xfffff78000000000;
44 #define KUSD_OFFSET_SUITE_MASK 0x2d0
45 #define KUSD_OFFSET_PRODUCT_TYPE 0x264
48 s ? printf(#s" = 0x%016"PRIx64"\n", s) :\
58 assert(size % sizeof(uint64_t) == 0); in kdbg_decode()
59 for (i = 0; i < size / sizeof(uint64_t); i++) { in kdbg_decode()
80 &kdbg_hdr, sizeof(kdbg_hdr), 0)) { in get_kdbg()
96 if (!va_space_rw(vs, KiWaitNever, &kwn, sizeof(kwn), 0) || in get_kdbg()
[all …]
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| /qemu/hw/misc/ |
| H A D | aspeed_i3c.c | 21 REG32(I3C1_REG0, 0x10)
22 REG32(I3C1_REG1, 0x14)
23 FIELD(I3C1_REG1, I2C_MODE, 0, 1)
25 REG32(I3C2_REG0, 0x20)
26 REG32(I3C2_REG1, 0x24)
27 FIELD(I3C2_REG1, I2C_MODE, 0, 1)
29 REG32(I3C3_REG0, 0x30)
30 REG32(I3C3_REG1, 0x34)
31 FIELD(I3C3_REG1, I2C_MODE, 0, 1)
33 REG32(I3C4_REG0, 0x40)
[all …]
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| /qemu/hw/arm/ |
| H A D | musca.c | 110 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); in OBJECT_DECLARE_TYPE()
150 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); in make_unimp_dev()
170 .addr = 0x00200000,
171 .size = 0x00800000,
175 .addr = 0x00000000,
176 .size = 0x00200000,
183 .addr = 0x00000000,
184 .size = 0x02000000,
188 .addr = 0x0a400000,
189 .size = 0x00080000,
[all …]
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| /qemu/hw/net/ |
| H A D | sunhme.c | 38 #define HME_REG_SIZE 0x8000
40 #define HME_SEB_REG_SIZE 0x2000
42 #define HME_SEBI_RESET 0x0
43 #define HME_SEB_RESET_ETX 0x1
44 #define HME_SEB_RESET_ERX 0x2
46 #define HME_SEBI_STAT 0x100
47 #define HME_SEBI_STAT_LINUXBUG 0x108
48 #define HME_SEB_STAT_RXTOHOST 0x10000
49 #define HME_SEB_STAT_NORXD 0x20000
50 #define HME_SEB_STAT_MIFIRQ 0x800000
[all …]
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| /qemu/target/sh4/ |
| H A D | translate.c | 98 for (i = 0; i < 24; i++) { in sh4_translate_init()
154 for (i = 0; i < 32; i++) in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
167 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
169 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
171 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
172 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
177 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
180 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
183 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
[all …]
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| /qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 38 #define PCI_VENDOR_ID 0x00 /* 16 bits */
39 #define PCI_DEVICE_ID 0x02 /* 16 bits */
40 #define PCI_COMMAND 0x04 /* 16 bits */
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
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| /qemu/target/s390x/tcg/ |
| H A D | insn-data.h.inc | 26 C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
27 C(0xb9f8, ARK, RRF_a, DO, r2, r3, new, r1_32, add, adds32)
28 C(0x5a00, A, RX_a, Z, r1, m2_32s, new, r1_32, add, adds32)
29 C(0xe35a, AY, RXY_a, LD, r1, m2_32s, new, r1_32, add, adds32)
30 C(0xb908, AGR, RRE, Z, r1, r2, r1, 0, add, adds64)
31 C(0xb918, AGFR, RRE, Z, r1, r2_32s, r1, 0, add, adds64)
32 C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
33 C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
34 C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
35 F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP)
[all …]
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| /qemu/target/xtensa/core-lx106/ |
| H A D | xtensa-modules.c.inc | 31 { "MMID", 89, 0 },
32 { "DDR", 104, 0 },
33 { "176", 176, 0 },
34 { "208", 208, 0 },
35 { "INTERRUPT", 226, 0 },
36 { "INTCLEAR", 227, 0 },
37 { "CCOUNT", 234, 0 },
38 { "PRID", 235, 0 },
39 { "ICOUNT", 236, 0 },
40 { "CCOMPARE0", 240, 0 },
[all …]
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| /qemu/disas/ |
| H A D | m68k.c | 35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]
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| H A D | nanomips.c | 62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
123 sizeof(register_list) / sizeof(register_list[0]), info); in decode_gpr_gpr4()
132 * 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
[all …]
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| /qemu/linux-user/ |
| H A D | syscall.c | 153 #define CLONE_IO 0x80000000 /* Clone io context */
179 # define CLONE_PIDFD 0x00001000
204 * (The one remaining unallocated bit is 0x1000 which used to be CLONE_PID.)
462 #if TARGET_O_LARGEFILE != 0 || O_LARGEFILE != 0
493 if (flags == 0) {
537 for (k = 0; k < ARRAY_SIZE(g_posix_timer_allocated); k++) { in next_free_host_timer()
538 if (qatomic_xchg(g_posix_timer_allocated + k, 1) == 0) { in next_free_host_timer()
547 qatomic_store_release(g_posix_timer_allocated + id, 0); in free_host_timer_slot()
604 if (b != 0) { in check_zeroed_user()
605 return 0; in check_zeroed_user()
[all …]
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| /qemu/target/xtensa/core-de233_fpu/ |
| H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
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| /qemu/target/xtensa/core-sample_controller/ |
| H A D | xtensa-modules.c.inc | 32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
[all …]
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| /qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "PTEVADDR", 83, 0 },
36 { "DDR", 104, 0 },
37 { "CONFIGID0", 176, 0 },
38 { "CONFIGID1", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]
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| /qemu/target/xtensa/core-dc233c/ |
| H A D | xtensa-modules.c.inc | 3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
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| /qemu/target/xtensa/core-de212/ |
| H A D | xtensa-modules.c.inc | 32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
[all …]
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| /qemu/target/xtensa/core-dc232b/ |
| H A D | xtensa-modules.c.inc | 29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
[all …]
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| /qemu/target/xtensa/core-test_kc705_be/ |
| H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
|