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/linux-3.3/arch/arm/mach-footbridge/include/mach/
Dhardware.h16 * 0xff800000 0x40000000 1MB X-Bus
17 * 0xff000000 0x7c000000 1MB PCI I/O space
18 * 0xfe000000 0x42000000 1MB CSR
19 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
20 * 0xfc000000 0x79000000 1MB PCI IACK/special space
21 * 0xfb000000 0x7a000000 16MB PCI Config type 1
22 * 0xfa000000 0x7b000000 16MB PCI Config type 0
23 * 0xf9000000 0x50000000 1MB Cache flush
24 * 0xf0000000 0x80000000 16MB ISA memory
33 #define XBUS_SIZE 0x00100000
[all …]
Ddebug-macro.S19 mov \rp, #0x000003f8
20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rp, \rp, #0x7c000000 @ physical
24 #define UART_SHIFT 0
31 .equ dc21285_high, ARMCSR_BASE & 0xff000000
32 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
38 mov \rp, #0
41 orr \rp, \rp, #0x42000000
45 str \rd, [\rx, #0x160] @ UARTDR
49 1001: ldr \rd, [\rx, #0x178] @ UARTFLG
/linux-3.3/arch/powerpc/platforms/44x/
Dcanyonlands.c34 #define BCSR_USB_EN 0x11
48 return 0; in ppc460ex_device_probe()
61 return 0; in ppc460ex_probe()
71 int ret = 0; in ppc460ex_canyonlands_fixup()
79 bcsr = of_iomap(np, 0); in ppc460ex_canyonlands_fixup()
94 vaddr = of_iomap(np, 0); in ppc460ex_canyonlands_fixup()
117 setbits32((vaddr + GPIO0_OSRH), 0x42000000); in ppc460ex_canyonlands_fixup()
118 setbits32((vaddr + GPIO0_TSRH), 0x42000000); in ppc460ex_canyonlands_fixup()
/linux-3.3/arch/powerpc/boot/dts/
Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
Dlite5200b.dts20 reg = <0x00000000 0x10000000>; // 256MB
30 cell-index = <0>;
76 phy0: ethernet-phy@0 {
77 reg = <0>;
84 reg = <0x50>;
90 reg = <0x8000 0x4000>;
95 interrupt-map-mask = <0xf800 0 0 7>;
96 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
97 0xc000 0 0 2 &mpc5200_pic 1 1 3
98 0xc000 0 0 3 &mpc5200_pic 1 2 3
[all …]
Dmpc8349emitx.dts31 #size-cells = <0>;
33 PowerPC,8349@0 {
35 reg = <0x0>;
40 timebase-frequency = <0>; // from bootloader
41 bus-frequency = <0>; // from bootloader
42 clock-frequency = <0>; // from bootloader
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x00100000>;
57 reg = <0xe0000000 0x00000200>;
58 bus-frequency = <0>; // from bootloader
[all …]
Dmedia5200.dts30 PowerPC,5200@0 {
38 reg = <0x00000000 0x08000000>; // 128MB RAM
78 phy0: ethernet-phy@0 {
79 reg = <0>;
84 reg = <0x1000 0x100>;
89 interrupt-map-mask = <0xf800 0 0 7>;
90 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
91 0xc000 0 0 2 &media5200_fpga 0 3
92 0xc000 0 0 3 &media5200_fpga 0 4
93 0xc000 0 0 4 &media5200_fpga 0 5
[all …]
Ddigsy_mtc.dts21 reg = <0x00000000 0x02000000>; // 32MB
41 msp430@0 {
44 reg = <0>;
77 phy0: ethernet-phy@0 {
78 reg = <0>;
85 reg = <0x50>;
90 reg = <0x56>;
95 reg = <0x68>;
105 interrupt-map-mask = <0xf800 0 0 7>;
106 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
[all …]
Dpcm030.dts64 cell-index = <0>;
95 phy0: ethernet-phy@0 {
96 reg = <0>;
103 reg = <0x51>;
107 reg = <0x52>;
114 reg = <0x8000 0x4000>;
119 interrupt-map-mask = <0xf800 0 0 7>;
120 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
121 0xc000 0 0 2 &mpc5200_pic 1 1 3
122 0xc000 0 0 3 &mpc5200_pic 1 2 3
[all …]
Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
Dmpc834x_mds.dts31 #size-cells = <0>;
33 PowerPC,8349@0 {
35 reg = <0x0>;
40 timebase-frequency = <0>; // from bootloader
41 bus-frequency = <0>; // from bootloader
42 clock-frequency = <0>; // from bootloader
48 reg = <0x00000000 0x10000000>; // 256MB at 0
53 reg = <0xe2400000 0x8000>;
61 ranges = <0x0 0xe0000000 0x00100000>;
62 reg = <0xe0000000 0x00000200>;
[all …]
Dmakalu.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
[all …]
Dpcm032.dts22 reg = <0x00000000 0x08000000>; // 128MB
52 reg = <0x660 0x10>;
53 interrupts = <1 15 0>;
65 cell-index = <0>;
96 phy0: ethernet-phy@0 {
97 reg = <0>;
104 reg = <0x51>;
108 reg = <0x52>;
115 interrupt-map-mask = <0xf800 0 0 7>;
116 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
[all …]
Dkilauea.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
[all …]
Dtqm5200.dts24 #size-cells = <0>;
26 PowerPC,5200@0 {
28 reg = <0>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
41 reg = <0x00000000 0x04000000>; // 64MB
48 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dmucmc52.dts21 gpt0: timer@600 { // GPT 0 in GPIO mode
106 phy0: ethernet-phy@0 {
108 reg = <0>;
119 reg = <0x2c>;
123 reg = <0x51>;
129 interrupt-map-mask = <0xf800 0 0 7>;
131 /* IDSEL 0x10 */
132 0x8000 0 0 1 &mpc5200_pic 0 3 3
133 0x8000 0 0 2 &mpc5200_pic 0 3 3
134 0x8000 0 0 3 &mpc5200_pic 0 2 3
[all …]
Dcharon.dts27 #size-cells = <0>;
29 PowerPC,5200@0 {
31 reg = <0>;
34 d-cache-size = <0x4000>; // L1, 16K
35 i-cache-size = <0x4000>; // L1, 16K
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x08000000>; // 128MB
51 ranges = <0 0xf0000000 0x0000c000>;
[all …]
/linux-3.3/arch/arm/mach-davinci/include/mach/
Ddm646x.h21 #define DM646X_EMAC_BASE (0x01C80000)
22 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
23 #define DM646X_EMAC_CNTRL_OFFSET (0x0000)
24 #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
25 #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
26 #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
28 #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
29 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
/linux-3.3/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt13 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
15 /* IDSEL 0x0E -mini PCI */
16 0x7000 0x0 0x0 0x1 &ipic 18 0x8
17 0x7000 0x0 0x0 0x2 &ipic 18 0x8
18 0x7000 0x0 0x0 0x3 &ipic 18 0x8
19 0x7000 0x0 0x0 0x4 &ipic 18 0x8
21 /* IDSEL 0x0F - PCI slot */
22 0x7800 0x0 0x0 0x1 &ipic 17 0x8
23 0x7800 0x0 0x0 0x2 &ipic 18 0x8
24 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/linux-3.3/arch/arm/mach-gemini/include/mach/
Dhardware.h19 # define GEMINI_DRAM_BASE 0x00000000
20 # define GEMINI_SRAM_BASE 0x70000000
22 # define GEMINI_SRAM_BASE 0x00000000
23 # define GEMINI_DRAM_BASE 0x10000000
25 #define GEMINI_FLASH_BASE 0x30000000
26 #define GEMINI_GLOBAL_BASE 0x40000000
27 #define GEMINI_WAQTCHDOG_BASE 0x41000000
28 #define GEMINI_UART_BASE 0x42000000
29 #define GEMINI_TIMER_BASE 0x43000000
30 #define GEMINI_LCD_BASE 0x44000000
[all …]
/linux-3.3/arch/arm/include/asm/hardware/
Ddec21285.h12 #define DC21285_PCI_IACK 0x79000000
13 #define DC21285_ARMCSR_BASE 0x42000000
14 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
15 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
16 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
17 #define DC21285_FLASH 0x41000000
18 #define DC21285_PCI_IO 0x7c000000
19 #define DC21285_PCI_MEM 0x80000000
28 #define CSR_PCICMD DC21285_IO(0x0004)
29 #define CSR_CLASSREV DC21285_IO(0x0008)
[all …]

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