Searched +full:0 +full:x4080 (Results 1 – 25 of 71) sorted by relevance
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74 first child APLIC domain assigned child index 0. The APLIC domain child130 reg = <0xc000000 0x4080>;142 reg = <0xd000000 0x4080>;152 reg = <0xe000000 0x4080>;[all...]
6 #define HOST1X_COMMON_OFA_MLOCK 0x40507 #define HOST1X_COMMON_NVJPG1_MLOCK 0x40708 #define HOST1X_COMMON_VIC_MLOCK 0x40789 #define HOST1X_COMMON_NVENC_MLOCK 0x407c10 #define HOST1X_COMMON_NVDEC_MLOCK 0x408011 #define HOST1X_COMMON_NVJPG_MLOCK 0x4084
36 reg = <0x4080 0x4>;41 mux-reg-masks = <0x0 0x3>; /* lane select */
49 "^mux-controller@[0-9a-f]+$":54 "^clock-controller@[0-9a-f]+$":60 "phy@[0-9a-f]+$":66 "^chipid@[0-9a-f]+$":72 "^pcie-ctrl@[0-9a-f]+$":77 "^clock@[0-9a-f]+$":83 "^dss-oldi-io-ctrl@[0-9a-f]+$":102 reg = <0x00100000 0x1c000>;109 reg = <0x0000408[all...]
12 #size-cells = <0>;14 cpu0: cpu@0 {17 reg = <0x0 0x0>;24 reg = <0x0 0x100>;31 reg = <0x0 0x200>;38 reg = <0x0 0x30[all...]
16 #address-cells = <0x2>;17 #size-cells = <0x0>;54 reg = <0x0 0x100>;61 reg = <0x0 0x101>;68 reg = <0x0 0x102>;75 reg = <0x0 0x10[all...]
13 #size-cells = <0>;15 cpu0: cpu@0 {18 reg = <0x0 0x0>;25 reg = <0x0 0x1>;32 reg = <0x0 0x2>;39 reg = <0x0 0x[all...]
18 #size-cells = <0>;20 cpu0: cpu@0 {23 reg = <0x0 0x0>;30 reg = <0x0 0x1>;37 reg = <0x0 0x2>;44 reg = <0x0 0x[all...]
19 #size-cells = <0>;21 cpu0: cpu@0 {24 reg = <0x0 0x0>;31 reg = <0x0 0x1>;53 #clock-cells = <0>;67 reg = <0x0 0x07f50e00 0x[all...]
50 #define GEN3_IMBAR1SZ_OFFSET 0x00d051 #define GEN3_IMBAR2SZ_OFFSET 0x00d152 #define GEN3_EMBAR1SZ_OFFSET 0x00d253 #define GEN3_EMBAR2SZ_OFFSET 0x00d354 #define GEN3_DEVCTRL_OFFSET 0x009855 #define GEN3_DEVSTS_OFFSET 0x009a56 #define GEN3_UNCERRSTS_OFFSET 0x014c57 #define GEN3_CORERRSTS_OFFSET 0x015858 #define GEN3_LINK_STATUS_OFFSET 0x01a260 #define GEN3_NTBCNTL_OFFSET 0x000[all...]
32 #define XDMA_DESC_MAGIC 0xad4bUL34 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)35 #define XDMA_DESC_STOPPED BIT(0)75 #define XDMA_CHAN_IDENTIFIER 0x076 #define XDMA_CHAN_CONTROL 0x477 #define XDMA_CHAN_CONTROL_W1S 0x878 #define XDMA_CHAN_CONTROL_W1C 0xc79 #define XDMA_CHAN_STATUS 0x4080 #define XDMA_CHAN_STATUS_RC 0x4481 #define XDMA_CHAN_COMPLETED_DESC 0x4[all...]
8 #define TN40_REGS_SIZE 0x1000010 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */11 #define TN40_REG_TXD_CFG1_0 0x400012 #define TN40_REG_TXD_CFG1_1 0x400413 #define TN40_REG_TXD_CFG1_2 0x400814 #define TN40_REG_TXD_CFG1_3 0x400C16 #define TN40_REG_RXF_CFG1_0 0x401[all...]
1 rv515 0x6d402 0x1434 SRC_Y_X3 0x1438 DST_Y_X4 0x143C DST_HEIGHT_WIDTH5 0x146C DP_GUI_MASTER_CNTL6 0x1474 BRUSH_Y_X7 0x1478 DP_BRUSH_BKGD_CLR8 0x147C DP_BRUSH_FRGD_CLR9 0x1480 BRUSH_DATA010 0x148[all...]
23 #define MFC_PUT_CMD 0x2024 #define MFC_PUTS_CMD 0x2825 #define MFC_PUTR_CMD 0x3026 #define MFC_PUTF_CMD 0x2227 #define MFC_PUTB_CMD 0x2128 #define MFC_PUTFS_CMD 0x2A29 #define MFC_PUTBS_CMD 0x2930 #define MFC_PUTRF_CMD 0x3231 #define MFC_PUTRB_CMD 0x3132 #define MFC_PUTL_CMD 0x2[all...]
46 * -- The PCI Function Number to use in the PCI Device ID Table. "0"73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs97 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */102 CH_PCI_ID_TABLE_FENTRY(0x400[all...]
13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x000014 #define MX28_PAD_GPMI_D01__GPMI_D1 0x001015 #define MX28_PAD_GPMI_D02__GPMI_D2 0x002016 #define MX28_PAD_GPMI_D03__GPMI_D3 0x003017 #define MX28_PAD_GPMI_D04__GPMI_D4 0x004018 #define MX28_PAD_GPMI_D05__GPMI_D5 0x005019 #define MX28_PAD_GPMI_D06__GPMI_D6 0x006020 #define MX28_PAD_GPMI_D07__GPMI_D7 0x007021 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x010022 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x011[all...]
25 #define WM831X_RESET_ID 0x0026 #define WM831X_REVISION 0x0127 #define WM831X_PARENT_ID 0x400028 #define WM831X_SYSVDD_CONTROL 0x400129 #define WM831X_THERMAL_MONITORING 0x400230 #define WM831X_POWER_STATE 0x400331 #define WM831X_WATCHDOG 0x400432 #define WM831X_ON_PIN_CONTROL 0x400533 #define WM831X_RESET_CONTROL 0x400634 #define WM831X_CONTROL_INTERFACE 0x400[all...]
24 #define ADAU1781_DMIC_BEEP_CTRL 0x400825 #define ADAU1781_LEFT_PGA 0x400e26 #define ADAU1781_RIGHT_PGA 0x400f27 #define ADAU1781_LEFT_PLAYBACK_MIXER 0x401c28 #define ADAU1781_RIGHT_PLAYBACK_MIXER 0x401e29 #define ADAU1781_MONO_PLAYBACK_MIXER 0x401f30 #define ADAU1781_LEFT_LINEOUT 0x402531 #define ADAU1781_RIGHT_LINEOUT 0x402632 #define ADAU1781_SPEAKER 0x402733 #define ADAU1781_BEEP_ZC 0x402[all...]
34 #define TC_NBLANK 0x408035 #define TC_WEN 0x408836 #define TC_REN 0x408c37 #define TC_FBEN 0x409038 #define TC_PRR 0x40ea41 #define RR_CLEAR 0x042 #define RR_COPY 0x343 #define RR_NOOP 0x544 #define RR_XOR 0x[all...]
58 * 00 00 Byte 1110 0x00059 * 01 00 Byte 1101 0x02060 * 10 00 Byte 1011 0x04061 * 11 00 Byte 0111 0x06063 * 00 01 Word 1100 0x00864 * 01 01 Word 1001 0x028 <= Not supported in this code.65 * 10 01 Word 0011 0x04867 * 00 10 Tribyte 1000 0x01068 * 01 10 Tribyte 0001 0x03070 * 10 11 Longword 0000 0x05[all...]
12 serdes_refclk: clk-0 {14 #clock-cells = <0>;15 clock-frequency = <0>;22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;39 reg = <0x0f000000 0x0001000[all...]
12 HNS_OP_RESET_FUNC = 0x1,13 HNS_OP_SERDES_LP_FUNC = 0x2,14 HNS_OP_LED_SET_FUNC = 0x3,15 HNS_OP_GET_PORT_TYPE_FUNC = 0x4,16 HNS_OP_GET_SFP_STAT_FUNC = 0x5,17 HNS_OP_LOCATE_LED_SET_FUNC = 0x6,21 HNS_DSAF_RESET_FUNC = 0x1,22 HNS_PPE_RESET_FUNC = 0x2,23 HNS_XGE_RESET_FUNC = 0x4,24 HNS_GE_RESET_FUNC = 0x[all...]
53 #define LBCIF_DWORD0_GROUP 0xAC54 #define LBCIF_DWORD1_GROUP 0xB057 #define LBCIF_ADDRESS_REGISTER 0xAC58 #define LBCIF_DATA_REGISTER 0xB059 #define LBCIF_CONTROL_REGISTER 0xB160 #define LBCIF_STATUS_REGISTER 0xB263 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x0164 #define LBCIF_CONTROL_PAGE_WRITE 0x0265 #define LBCIF_CONTROL_EEPROM_RELOAD 0x0866 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x2[all...]
4 "Counter": "0,1,2,3",5 "EventCode": "0xB7, 0xBB",7 "MSRIndex": "0x1a6,0x1a7",8 "MSRValue": "0x6011",10 "UMask": "0x1"14 "Counter": "0,1,2,3",15 "EventCode": "0xB7, 0xB2 { global() object [all...]
4 "Counter": "0,1,2,3",5 "EventCode": "0x5",8 "UMask": "0x2"12 "Counter": "0,1,2,3",13 "EventCode": "0xB7, 0xBB",15 "MSRIndex": "0x1a6,0x1a7",16 "MSRValue": "0x3011",18 "UMask": "0x2 { global() object [all...]