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Searched +full:0 +full:x2008 (Results 1 – 13 of 13) sorted by relevance

/qemu/hw/usb/
H A Dquirks-pl2303-ids.h11 #define BENQ_VENDOR_ID 0x04a5
12 #define BENQ_PRODUCT_ID_S81 0x4027
14 #define PL2303_VENDOR_ID 0x067b
15 #define PL2303_PRODUCT_ID 0x2303
16 #define PL2303_PRODUCT_ID_RSAQ2 0x04bb
17 #define PL2303_PRODUCT_ID_DCU11 0x1234
18 #define PL2303_PRODUCT_ID_PHAROS 0xaaa0
19 #define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
20 #define PL2303_PRODUCT_ID_ALDIGA 0x0611
21 #define PL2303_PRODUCT_ID_MMX 0x0612
[all …]
H A Ddev-mtp.c50 CMD_GET_DEVICE_INFO = 0x1001,
51 CMD_OPEN_SESSION = 0x1002,
52 CMD_CLOSE_SESSION = 0x1003,
53 CMD_GET_STORAGE_IDS = 0x1004,
54 CMD_GET_STORAGE_INFO = 0x1005,
55 CMD_GET_NUM_OBJECTS = 0x1006,
56 CMD_GET_OBJECT_HANDLES = 0x1007,
57 CMD_GET_OBJECT_INFO = 0x1008,
58 CMD_GET_OBJECT = 0x1009,
59 CMD_DELETE_OBJECT = 0x100b,
[all …]
/qemu/hw/i386/
H A Damd_iommu.h29 #define AMDVI_CAPAB_BAR_LOW 0x04
30 #define AMDVI_CAPAB_BAR_HIGH 0x08
31 #define AMDVI_CAPAB_RANGE 0x0C
32 #define AMDVI_CAPAB_MISC 0x10
34 #define AMDVI_CAPAB_SIZE 0x18
35 #define AMDVI_CAPAB_REG_SIZE 0x04
38 #define AMDVI_CAPAB_ID_SEC 0xf
51 #define AMDVI_MMIO_DEVICE_TABLE 0x0000
52 #define AMDVI_MMIO_COMMAND_BASE 0x0008
53 #define AMDVI_MMIO_EVENT_BASE 0x0010
[all …]
/qemu/include/hw/ppc/
H A Dspapr_nested.h7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x07FF */
15 #define GSB_L0_GUEST_HEAP_INUSE 0x0800 /* Guest Management Heap Size */
16 #define GSB_L0_GUEST_HEAP_MAX 0x0801 /* Guest Management Heap Max Size */
[all …]
/qemu/hw/misc/
H A Dexynos4210_pmu.c35 #define DEBUG_PMU 0
39 #define DEBUG_PMU_EXTEND 0
46 } while (0)
52 } while (0)
54 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
58 #define PRINT_DEBUG(fmt, args...) do {} while (0)
59 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
65 #define OM_STAT 0x0000 /* OM status register */
66 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */
67 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */
[all …]
/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/sh4/
H A Dtranslate.c98 for (i = 0; i < 24; i++) { in sh4_translate_init()
154 for (i = 0; i < 32; i++) in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
167 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
169 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
171 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
172 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
177 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
180 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
183 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
[all …]
/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/disas/
H A Dm68k.c35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]