Lines Matching +full:0 +full:x2008
29 #define AMDVI_CAPAB_BAR_LOW 0x04
30 #define AMDVI_CAPAB_BAR_HIGH 0x08
31 #define AMDVI_CAPAB_RANGE 0x0C
32 #define AMDVI_CAPAB_MISC 0x10
34 #define AMDVI_CAPAB_SIZE 0x18
35 #define AMDVI_CAPAB_REG_SIZE 0x04
38 #define AMDVI_CAPAB_ID_SEC 0xf
51 #define AMDVI_MMIO_DEVICE_TABLE 0x0000
52 #define AMDVI_MMIO_COMMAND_BASE 0x0008
53 #define AMDVI_MMIO_EVENT_BASE 0x0010
54 #define AMDVI_MMIO_CONTROL 0x0018
55 #define AMDVI_MMIO_EXCL_BASE 0x0020
56 #define AMDVI_MMIO_EXCL_LIMIT 0x0028
57 #define AMDVI_MMIO_EXT_FEATURES 0x0030
58 #define AMDVI_MMIO_COMMAND_HEAD 0x2000
59 #define AMDVI_MMIO_COMMAND_TAIL 0x2008
60 #define AMDVI_MMIO_EVENT_HEAD 0x2010
61 #define AMDVI_MMIO_EVENT_TAIL 0x2018
62 #define AMDVI_MMIO_STATUS 0x2020
63 #define AMDVI_MMIO_PPR_BASE 0x0038
64 #define AMDVI_MMIO_PPR_HEAD 0x2030
65 #define AMDVI_MMIO_PPR_TAIL 0x2038
67 #define AMDVI_MMIO_SIZE 0x4000
77 #define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f
79 #define AMDVI_MMIO_CMDBUF_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f)
85 #define AMDVI_MMIO_EVTLOG_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f)
94 #define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0)
97 #define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff
100 #define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0)
112 #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0)
114 #define AMDVI_CMDBUF_ID_BYTE 0x07
117 #define AMDVI_CMD_COMPLETION_WAIT 0x01
118 #define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02
119 #define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03
120 #define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04
121 #define AMDVI_CMD_INVAL_INTR_TABLE 0x05
122 #define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06
123 #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07
124 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08
128 /* Device table entry bits 0:63 */
129 #define AMDVI_DEV_VALID (1ULL << 0)
131 #define AMDVI_DEV_MODE_MASK 0x7
133 #define AMDVI_DEV_PT_ROOT_MASK 0xffffffffff000
143 #define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12)
144 #define AMDVI_EVENT_IOPF (0x2U << 12)
146 #define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12)
147 #define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12)
148 #define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12)
149 #define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12)
152 #define AMDVI_PERM_READ (1 << 0)
155 #define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */
165 #define AMDVI_DTE_LOWER_QUAD_RESERVED 0x80300000000000fc
166 #define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100
167 #define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000
190 #define AMDVI_BASE_ADDR 0xfed80000ULL
212 #define AMDVI_INT_ADDR_FIRST 0xfee00000
213 #define AMDVI_INT_ADDR_LAST 0xfeefffff
217 #define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
220 #define AMDVI_IR_ERR 0x1
221 #define AMDVI_IR_GET_IRTE 0x2
222 #define AMDVI_IR_TARGET_ABORT 0x3
227 #define AMDVI_IR_INTCTL_ABORT 0
233 /* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */
234 #define AMDVI_IRTE_OFFSET 0x7ff
237 #define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0
238 #define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1
239 #define AMDVI_IOAPIC_INT_TYPE_SMI 0x2
240 #define AMDVI_IOAPIC_INT_TYPE_NMI 0x4
241 #define AMDVI_IOAPIC_INT_TYPE_INIT 0x5
242 #define AMDVI_IOAPIC_INT_TYPE_EINT 0x7