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/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux-6.8/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/linux-6.8/arch/arm/boot/dts/samsung/
Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/cache/
Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/linux-6.8/arch/arm/boot/dts/mediatek/
Dmt6580.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10008000 0x80>;
[all …]
Dmt6582.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x2>;
37 reg = <0x3>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
61 reg = <0x10008000 0x80>;
[all …]
Dmt6589.dtsi19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
30 reg = <0x1>;
35 reg = <0x2>;
40 reg = <0x3>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
78 reg = <0x10008000 0x80>;
[all …]
/linux-6.8/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dvga.c30 return nvkm_rd08(device, 0x601000 + port); in nvkm_rdport()
32 if (port == 0x03c0 || port == 0x03c1 || /* AR */ in nvkm_rdport()
33 port == 0x03c2 || port == 0x03da || /* INP0 */ in nvkm_rdport()
34 port == 0x03d4 || port == 0x03d5) /* CR */ in nvkm_rdport()
35 return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port); in nvkm_rdport()
37 if (port == 0x03c2 || port == 0x03cc || /* MISC */ in nvkm_rdport()
38 port == 0x03c4 || port == 0x03c5 || /* SR */ in nvkm_rdport()
39 port == 0x03ce || port == 0x03cf) { /* GR */ in nvkm_rdport()
41 head = 0; /* CR44 selects head */ in nvkm_rdport()
42 return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port); in nvkm_rdport()
[all …]
/linux-6.8/arch/arm64/boot/dts/nuvoton/
Dnuvoton-common-npcm8xx.dtsi22 reg = <0x0 0xf0800000 0x0 0x1000>;
27 reg = <0x0 0xdfff9000 0x0 0x1000>,
28 <0x0 0xdfffa000 0x0 0x2000>,
29 <0x0 0xdfffc000 0x0 0x2000>,
30 <0x0 0xdfffe000 0x0 0x2000>;
34 #address-cells = <0>;
36 ppi_cluster0: interrupt-partition-0 {
52 reg = <0x0 0xf0801000 0x0 0x78>;
60 reg = <0x0 0xf0801000 0x0 0x1000>;
68 ranges = <0x0 0x0 0xf0000000 0x00300000>,
[all …]
/linux-6.8/arch/arm64/boot/dts/freescale/
Ds32g2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x100>;
48 reg = <0x101>;
86 soc@0 {
90 ranges = <0 0 0 0x80000000>;
95 reg = <0x401c8000 0x3000>;
103 reg = <0x401cc000 0x3000>;
[all …]
Ds32v234.dtsi9 /memreserve/ 0x80000000 0x00010000;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0x0 0x0>;
31 cpu-release-addr = <0x0 0x80000000>;
38 reg = <0x0 0x1>;
40 cpu-release-addr = <0x0 0x80000000>;
47 reg = <0x0 0x100>;
49 cpu-release-addr = <0x0 0x80000000>;
56 reg = <0x0 0x101>;
[all …]
/linux-6.8/include/linux/mfd/madera/
Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux-6.8/drivers/gpu/drm/amd/display/dc/basics/
Ddc_common.c87 && plane_state->coeff_reduction_factor.value != 0) { in build_prescale_params()
96 bias_and_scale->scale_blue = 0x2000; in build_prescale_params()
97 bias_and_scale->scale_red = 0x2000; in build_prescale_params()
98 bias_and_scale->scale_green = 0x2000; in build_prescale_params()
/linux-6.8/arch/arm/boot/dts/ti/omap/
Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
Doss_3_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux-6.8/arch/powerpc/platforms/52xx/
Dmpc52xx_sleep.S14 ori r7, r7, 0x8000 /* EE */
18 li r10, 0 /* flag that irq handler sets */
21 lwz r8, 0x14(r6) /* intr->main_mask */
22 ori r8, r8, 0x1
23 xori r8, r8, 0x1
24 stw r8, 0x14(r6)
28 li r8, 0x1
29 stw r8, 0x40(r6) /* intr->main_emulate */
39 ori r10, r10, 0x2000
55 ori r10, r10, 0x2000
[all …]
/linux-6.8/arch/arm64/boot/dts/mediatek/
Dmt6755.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0x000>;
36 reg = <0x001>;
43 reg = <0x002>;
50 reg = <0x003>;
57 reg = <0x100>;
64 reg = <0x101>;
71 reg = <0x102>;
78 reg = <0x103>;
[all …]
/linux-6.8/arch/arc/boot/dts/
Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
/linux-6.8/arch/arm/boot/dts/intel/ixp/
Dintel-ixp42x-gateworks-gw2348.dts18 memory@0 {
20 reg = <0x00000000 0x4000000>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
68 flash@0,0 {
74 reg = <0 0x00000000 0x1000000>;
78 /* Eraseblock at 0x0fe0000 */
79 fis-index-block = <0x7f>;
[all …]
/linux-6.8/arch/arm64/boot/dts/amlogic/
Damlogic-c3.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x0 0x0>;
25 reg = <0x0 0x1>;
47 #clock-cells = <0>;
68 #address-cells = <0>;
70 reg = <0x0 0xfff01000 0 0x1000>,
71 <0x0 0xfff02000 0 0x2000>,
72 <0x0 0xfff04000 0 0x2000>,
73 <0x0 0xfff06000 0 0x2000>;
[all …]
/linux-6.8/arch/arm64/boot/dts/ti/
Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]

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