30 		return nvkm_rd08(device, 0x601000 + port);  in nvkm_rdport()
32 	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */  in nvkm_rdport()
33 	    port == 0x03c2 || port == 0x03da ||	/* INP0 */  in nvkm_rdport()
34 	    port == 0x03d4 || port == 0x03d5)	/* CR */  in nvkm_rdport()
35 		return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port);  in nvkm_rdport()
37 	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */  in nvkm_rdport()
38 	    port == 0x03c4 || port == 0x03c5 ||	/* SR */  in nvkm_rdport()
39 	    port == 0x03ce || port == 0x03cf) {	/* GR */  in nvkm_rdport()
41 			head = 0; /* CR44 selects head */  in nvkm_rdport()
42 		return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port);  in nvkm_rdport()
45 	return 0x00;  in nvkm_rdport()
52 		nvkm_wr08(device, 0x601000 + port, data);  in nvkm_wrport()
54 	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */  in nvkm_wrport()
55 	    port == 0x03c2 || port == 0x03da ||	/* INP0 */  in nvkm_wrport()
56 	    port == 0x03d4 || port == 0x03d5)	/* CR */  in nvkm_wrport()
57 		nvkm_wr08(device, 0x601000 + (head * 0x2000) + port, data);  in nvkm_wrport()
59 	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */  in nvkm_wrport()
60 	    port == 0x03c4 || port == 0x03c5 ||	/* SR */  in nvkm_wrport()
61 	    port == 0x03ce || port == 0x03cf) {	/* GR */  in nvkm_wrport()
63 			head = 0; /* CR44 selects head */  in nvkm_wrport()
64 		nvkm_wr08(device, 0x0c0000 + (head * 0x2000) + port, data);  in nvkm_wrport()
71 	nvkm_wrport(device, head, 0x03c4, index);  in nvkm_rdvgas()
72 	return nvkm_rdport(device, head, 0x03c5);  in nvkm_rdvgas()
78 	nvkm_wrport(device, head, 0x03c4, index);  in nvkm_wrvgas()
79 	nvkm_wrport(device, head, 0x03c5, value);  in nvkm_wrvgas()
85 	nvkm_wrport(device, head, 0x03ce, index);  in nvkm_rdvgag()
86 	return nvkm_rdport(device, head, 0x03cf);  in nvkm_rdvgag()
92 	nvkm_wrport(device, head, 0x03ce, index);  in nvkm_wrvgag()
93 	nvkm_wrport(device, head, 0x03cf, value);  in nvkm_wrvgag()
99 	nvkm_wrport(device, head, 0x03d4, index);  in nvkm_rdvgac()
100 	return nvkm_rdport(device, head, 0x03d5);  in nvkm_rdvgac()
106 	nvkm_wrport(device, head, 0x03d4, index);  in nvkm_wrvgac()
107 	nvkm_wrport(device, head, 0x03d5, value);  in nvkm_wrvgac()
113 	if (port == 0x03c4) return nvkm_rdvgas(device, head, index);  in nvkm_rdvgai()
114 	if (port == 0x03ce) return nvkm_rdvgag(device, head, index);  in nvkm_rdvgai()
115 	if (port == 0x03d4) return nvkm_rdvgac(device, head, index);  in nvkm_rdvgai()
116 	return 0x00;  in nvkm_rdvgai()
122 	if      (port == 0x03c4) nvkm_wrvgas(device, head, index, value);  in nvkm_wrvgai()
123 	else if (port == 0x03ce) nvkm_wrvgag(device, head, index, value);  in nvkm_wrvgai()
124 	else if (port == 0x03d4) nvkm_wrvgac(device, head, index, value);  in nvkm_wrvgai()
130 	bool locked = !nvkm_rdvgac(device, 0, 0x1f);  in nvkm_lockvgac()
131 	u8 data = lock ? 0x99 : 0x57;  in nvkm_lockvgac()
133 		nvkm_wrvgac(device, 0, 0x1f, data);  in nvkm_lockvgac()
135 		nvkm_wrvgac(device, 0, 0x3f, data);  in nvkm_lockvgac()
136 	if (device->chipset == 0x11) {  in nvkm_lockvgac()
137 		if (!(nvkm_rd32(device, 0x001084) & 0x10000000))  in nvkm_lockvgac()
138 			nvkm_wrvgac(device, 1, 0x1f, data);  in nvkm_lockvgac()
143 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
145  * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
147  * expected and values can be set for the appropriate head by using a 0x2000
150  * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
151  *    cr44 must be set to 0 or 3 for accessing values on the correct head
152  *    through the common 0xc03c* addresses
158  * 0 and 1 are treated as head values and so the set value is (owner * 3)
165 		if (device->chipset == 0x11) {  in nvkm_rdvgaowner()
166 			u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000;  in nvkm_rdvgaowner()
167 			if (tied == 0) {  in nvkm_rdvgaowner()
168 				u8 slA = nvkm_rdvgac(device, 0, 0x28) & 0x80;  in nvkm_rdvgaowner()
169 				u8 tvA = nvkm_rdvgac(device, 0, 0x33) & 0x01;  in nvkm_rdvgaowner()
170 				u8 slB = nvkm_rdvgac(device, 1, 0x28) & 0x80;  in nvkm_rdvgaowner()
171 				u8 tvB = nvkm_rdvgac(device, 1, 0x33) & 0x01;  in nvkm_rdvgaowner()
172 				if (slA && !tvA) return 0x00;  in nvkm_rdvgaowner()
173 				if (slB && !tvB) return 0x03;  in nvkm_rdvgaowner()
174 				if (slA) return 0x00;  in nvkm_rdvgaowner()
175 				if (slB) return 0x03;  in nvkm_rdvgaowner()
176 				return 0x00;  in nvkm_rdvgaowner()
178 			return 0x04;  in nvkm_rdvgaowner()
181 		return nvkm_rdvgac(device, 0, 0x44);  in nvkm_rdvgaowner()
184 	return 0x00;  in nvkm_rdvgaowner()
192 		if (device->chipset == 0x11) {  in nvkm_wrvgaowner()
194 			nvkm_rdvgac(device, 0, 0x1f);  in nvkm_wrvgaowner()
195 			nvkm_rdvgac(device, 1, 0x1f);  in nvkm_wrvgaowner()
198 		nvkm_wrvgac(device, 0, 0x44, owner);  in nvkm_wrvgaowner()
200 		if (device->chipset == 0x11) {  in nvkm_wrvgaowner()
201 			nvkm_wrvgac(device, 0, 0x2e, owner);  in nvkm_wrvgaowner()
202 			nvkm_wrvgac(device, 0, 0x2e, owner);  in nvkm_wrvgaowner()