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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqemu,virtual-cpufreq.yaml46 reg = <0x1040000 0x2000>;
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800pci.h29 #define FIRMWARE_IMAGE_BASE 0x2000
/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts5 #size-cells = <0x02>;
6 #address-cells = <0x02>;
16 #size-cells = <0x02>;
17 #address-cells = <0x02>;
21 memory@0 {
23 reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
28 #clock-cells = <0>;
35 #size-cells = <0x00>;
36 #address-cells = <0x01>;
47 os-support = <0>;
[all …]
/linux/include/soc/fsl/qe/
H A Ducc_fast.h21 #define R_E 0x80000000 /* buffer empty */
22 #define R_W 0x20000000 /* wrap bit */
23 #define R_I 0x10000000 /* interrupt on reception */
24 #define R_L 0x08000000 /* last */
25 #define R_F 0x04000000 /* first */
28 #define T_R 0x80000000 /* ready bit */
29 #define T_W 0x20000000 /* wrap bit */
30 #define T_I 0x10000000 /* interrupt on completion */
31 #define T_L 0x08000000 /* last */
34 #define R_E_S 0x8000 /* buffer empty */
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v6_0.c30 for (i = 0; i < 4; i++) in umc_v6_0_init_registers()
31 for (j = 0; j < 4; j++) in umc_v6_0_init_registers()
32 WREG32((i*0x100000 + 0x5010c + j*0x2000)/4, 0x1002); in umc_v6_0_init_registers()
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos990.dtsi30 #size-cells = <0>;
72 cpu0: cpu@0 {
75 reg = <0x0>;
82 reg = <0x1>;
89 reg = <0x2>;
96 reg = <0x3>;
103 reg = <0x4>;
110 reg = <0x5>;
117 reg = <0x6>;
124 reg = <0x7>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
/linux/sound/soc/codecs/
H A Duda1380.h11 #define UDA1380_CLK 0x00
12 #define UDA1380_IFACE 0x01
13 #define UDA1380_PM 0x02
14 #define UDA1380_AMIX 0x03
15 #define UDA1380_HP 0x04
16 #define UDA1380_MVOL 0x10
17 #define UDA1380_MIXVOL 0x11
18 #define UDA1380_MODE 0x12
19 #define UDA1380_DEEMP 0x13
20 #define UDA1380_MIXER 0x14
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml62 cell 0: index of dma channel mux instance.
66 cell 0: peripheral dma request id.
198 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
255 - const: tx-0-15
276 reg = <0x40018000 0x2000>,
277 <0x40024000 0x1000>,
278 <0x40025000 0x1000>;
279 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
280 <0 9 IRQ_TYPE_LEVEL_HIGH>;
294 reg = <0x40080000 0x2000>,
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet/
H A Dinstruction.json4 "EventCode": "0x100",
9 "EventCode": "0x200",
14 "EventCode": "0x400",
19 "EventCode": "0x800",
24 "EventCode": "0x1000",
29 "EventCode": "0x2000",
34 "EventCode": "0x4000",
39 "EventCode": "0x8000",
44 "EventCode": "0x10000",
49 "EventCode": "0x20000",
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/
H A Dinstruction.json4 "EventCode": "0x100",
9 "EventCode": "0x200",
14 "EventCode": "0x400",
19 "EventCode": "0x800",
24 "EventCode": "0x1000",
29 "EventCode": "0x2000",
34 "EventCode": "0x4000",
39 "EventCode": "0x8000",
44 "EventCode": "0x10000",
49 "EventCode": "0x20000",
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/p550/
H A Dinstruction.json4 "EventCode": "0x100",
9 "EventCode": "0x200",
14 "EventCode": "0x400",
19 "EventCode": "0x800",
24 "EventCode": "0x1000",
29 "EventCode": "0x2000",
34 "EventCode": "0x4000",
39 "EventCode": "0x8000",
44 "EventCode": "0x10000",
49 "EventCode": "0x20000",
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/
H A Dinstruction.json4 "EventCode": "0x100",
9 "EventCode": "0x200",
14 "EventCode": "0x400",
19 "EventCode": "0x800",
24 "EventCode": "0x1000",
29 "EventCode": "0x2000",
34 "EventCode": "0x4000",
39 "EventCode": "0x8000",
44 "EventCode": "0x10000",
49 "EventCode": "0x20000",
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/p650/
H A Dinstruction.json4 "EventCode": "0x100",
9 "EventCode": "0x200",
14 "EventCode": "0x400",
19 "EventCode": "0x800",
24 "EventCode": "0x1000",
29 "EventCode": "0x2000",
34 "EventCode": "0x4000",
39 "EventCode": "0x8000",
44 "EventCode": "0x10000",
49 "EventCode": "0x20000",
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dhi6220-clock.txt37 reg = <0x0 0xf7030000 0x0 0x2000>;
/linux/arch/arc/boot/dts/
H A Dnsim_700.dts17 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signal…
33 #clock-cells = <0>;
46 reg = <0xf0000000 0x2000>;
/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,g12a-usb2-phy.yaml37 const: 0
75 reg = <0x36000 0x2000>;
80 #phy-cells = <0>;
H A Damlogic,g12a-usb3-pcie-phy.yaml58 reg = <0x46000 0x2000>;
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wsa881x.yaml33 const: 0
36 const: 0
51 #size-cells = <0>;
52 reg = <0x0c2d0000 0x2000>;
54 speaker@0,1 {
56 reg = <0 1>;
57 powerdown-gpios = <&wcdpinctrl 2 0>;
58 #thermal-sensor-cells = <0>;
59 #sound-dai-cells = <0>;
62 speaker@0,2 {
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/linux/drivers/staging/gpib/include/
H A Damcc5920.h11 AMCC_INTCS_REG = 0x38,
12 AMCC_PASS_THRU_REG = 0x60,
16 AMCC_ADDON_INTR_ENABLE_BIT = 0x2000,
17 AMCC_ADDON_INTR_ACTIVE_BIT = 0x400000,
18 AMCC_INTR_ACTIVE_BIT = 0x800000,
25 return (num_wait_states & 0x7) << (--region * bits_per_region); in amcc_wait_state_bits()
29 PREFETCH_DISABLED = 0x0,
30 PREFETCH_SMALL = 0x8,
31 PREFETCH_MEDIUM = 0x10,
32 PREFETCH_LARGE = 0x18,
[all …]
/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h41 #define REG_PM_CTRLSTAT 0x44
43 #define REG_PCIE_CAP_LIST 0x58
45 #define REG_DEVICE_CAP 0x5C
46 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
47 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
49 #define REG_DEVICE_CTRL 0x60
50 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
52 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55 #define REG_VPD_CAP 0x6C
56 #define VPD_CAP_ID_MASK 0xff
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
/linux/drivers/net/phy/
H A Dmarvell-88x2222.c20 #define MV_PCS_CONFIG 0xF002
21 #define MV_PCS_HOST_XAUI 0x73
22 #define MV_PCS_LINE_10GBR (0x71 << 8)
23 #define MV_PCS_LINE_1GBX_AN (0x7B << 8)
24 #define MV_PCS_LINE_SGMII_AN (0x7F << 8)
27 #define MV_PORT_RST 0xF003
33 #define MV_RX_SIGNAL_DETECT 0x000A
34 #define MV_RX_SIGNAL_DETECT_GLOBAL BIT(0)
37 #define MV_1GBX_CTRL (0x2000 + MII_BMCR)
40 #define MV_1GBX_STAT (0x2000 + MII_BMSR)
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
34 d-cache-size = <0x8000>; /* 32 KiB */
37 i-cache-size = <0x8000>; /* 32 KiB */
46 reg = <0x0 0x1>;
48 d-cache-size = <0x8000>; /* 32 KiB */
51 i-cache-size = <0x8000>; /* 32 KiB */
60 reg = <0x0 0x2>;
62 d-cache-size = <0x8000>; /* 32 KiB */
[all …]

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