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/linux-6.15/include/linux/mfd/wm8350/
Dsupply.h17 #define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
18 #define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
19 #define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
22 * R168 (0xA8) - Battery Charger Control 1
24 #define WM8350_CHG_ENA_R168 0x8000
25 #define WM8350_CHG_THR 0x2000
26 #define WM8350_CHG_EOC_SEL_MASK 0x1C00
27 #define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
28 #define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
29 #define WM8350_CHG_RECOVER_T 0x0080
[all …]
/linux-6.15/Documentation/devicetree/bindings/pci/
Drcar-gen4-pci-ep.yaml100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
103 <0 0xfe000000 0 0x400000>;
Damd,versal2-mdb-host.yaml45 - const: 0
46 - const: 0
47 - const: 0
64 const: 0
96 reg = <0x0 0xed931000 0x0 0x2000>,
97 <0x1000 0x100000 0x0 0xff00000>,
98 <0x1000 0x0 0x0 0x1000>,
99 <0x0 0xed860000 0x0 0x2000>;
101 ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>,
102 <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
[all …]
/linux-6.15/arch/powerpc/include/asm/
Dhydra.h30 char Pad1[0x30];
34 char Pad2[0x7fc4];
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
44 char SCSI[0x1000];
[all …]
/linux-6.15/Documentation/devicetree/bindings/sound/
Dqcom,wcd939x.yaml76 #size-cells = <0>;
77 reg = <0x03210000 0x2000>;
78 wcd939x_rx: codec@0,4 {
80 reg = <0 4>;
87 #size-cells = <0>;
88 reg = <0x03230000 0x2000>;
89 wcd938x_tx: codec@0,3 {
91 reg = <0 3>;
/linux-6.15/arch/arm/boot/dts/ti/omap/
Domap3.dtsi34 #size-cells = <0>;
36 cpu@0 {
39 reg = <0x0>;
50 reg = <0x54000000 0x800000>;
85 reg = <0x68000000 0x10000>;
96 ranges = <0 0x48000000 0x1000000>;
100 reg = <0x2000 0x2000>;
103 ranges = <0 0x2000 0x2000>;
108 reg = <0x30 0x238>;
110 #size-cells = <0>;
[all …]
/linux-6.15/drivers/pcmcia/
Dtcic.h33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
/linux-6.15/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
/linux-6.15/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0 0x0>;
60 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
74 reg = <0x0 0x3>;
82 cpu_suspend = <0x84000001>;
83 cpu_off = <0x84000002>;
84 cpu_on = <0x84000003>;
89 #clock-cells = <0>;
[all …]
/linux-6.15/arch/arm/boot/dts/nxp/imx/
Dimx7d.dtsi17 cpu0: cpu@0 {
53 opp-supported-hw = <0xd>, <0x7>;
61 opp-supported-hw = <0xc>, <0x7>;
69 opp-supported-hw = <0x8>, <0x3>;
78 #phy-cells = <0>;
84 reg = <0x3007d000 0x1000>;
91 arm,primecell-periphid = <0xbb956>;
111 reg = <0x31001000 0x1000>,
112 <0x31002000 0x2000>,
113 <0x31004000 0x2000>,
[all …]
/linux-6.15/drivers/video/fbdev/
Dsmscufx.c35 ({ if (status < 0) pr_warn(fmt, ##args); })
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
55 #define UFX_IOCTL_RETURN_EDID (0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
100 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
111 .xpanstep = 0,
112 .ypanstep = 0,
[all …]
/linux-6.15/Documentation/devicetree/bindings/dma/ti/
Dk3-bcdma.yaml51 0 - split channel
57 if cell 1 is 0 (split channel):
60 for source thread IDs (rx): 0 - 0x7fff
61 for destination thread IDs (tx): 0x8000 - 0xffff
96 maximum: 0x3f
107 maximum: 0x3f
118 maximum: 0x3f
244 reg = <0x0 0x485c0100 0x0 0x100>,
245 <0x0 0x4c000000 0x0 0x20000>,
246 <0x0 0x4a820000 0x0 0x20000>,
[all …]
/linux-6.15/drivers/usb/gadget/udc/
Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml67 enum: [ 0, 1, 2 ]
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
82 bits[3:0] trigger type and level flags.
150 "^v2m@[0-9a-f]+$":
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
[all …]
/linux-6.15/drivers/media/common/b2c2/
Dflexcop-hw-filter.c30 v418.mac_address_418.MAC1 = mac[0]; in flexcop_set_mac_filter()
49 /* index_reg_310.extra_index_reg need to 0 or 7 to work */ in flexcop_pid_group_filter()
68 vpid.vregname.field = onoff ? pid : 0x1fff; \
78 Stream1_trans, 0); in flexcop_pid_Stream1_PID_ctrl()
85 Stream2_trans, 0); in flexcop_pid_Stream2_PID_ctrl()
91 pid_ctrl(pid_filter_304, PCR_PID, PCR_filter_sig, PCR_trans, 0); in flexcop_pid_PCR_PID_ctrl()
97 pid_ctrl(pid_filter_304, PMT_PID, PMT_filter_sig, PMT_trans, 0); in flexcop_pid_PMT_PID_ctrl()
103 pid_ctrl(pid_filter_308, EMM_PID, EMM_filter_sig, EMM_trans, 0); in flexcop_pid_EMM_PID_ctrl()
109 pid_ctrl(pid_filter_308, ECM_PID, ECM_filter_sig, ECM_trans, 0); in flexcop_pid_ECM_PID_ctrl()
115 if (pid == 0x2000) in flexcop_pid_control()
[all …]
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt7988a.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
21 reg = <0x0>;
32 reg = <0x1>;
43 reg = <0x2>;
54 reg = <0x3>;
63 cluster0_opp: opp-table-0 {
89 #clock-cells = <0>;
111 reg = <0 0x43000000 0 0x50000>;
124 reg = <0 0x0c000000 0 0x40000>, /* GICD */
[all …]
/linux-6.15/arch/mips/mti-malta/
Dmalta-init.c45 int baud = 0; in console_config()
46 char parity = '\0', bits = '\0', flow = '\0'; in console_config()
51 while (*s >= '0' && *s <= '9') in console_config()
52 baud = baud*10 + *s++ - '0'; in console_config()
66 if (baud == 0) in console_config()
72 if (flow == '\0') in console_config()
76 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, in console_config()
95 (void *)(CAC_BASE + 0xa80) : in mips_nmi_setup()
96 (void *)(CAC_BASE + 0x380); in mips_nmi_setup()
97 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
[all …]
/linux-6.15/drivers/net/ethernet/ti/
Dtlan.h40 #define TLAN_IGNORE 0
47 } while (0)
49 #define TLAN_DEBUG_GNRL 0x0001
50 #define TLAN_DEBUG_TX 0x0002
51 #define TLAN_DEBUG_RX 0x0004
52 #define TLAN_DEBUG_LIST 0x0008
53 #define TLAN_DEBUG_PROBE 0x0010
65 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
66 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
68 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
[all …]
/linux-6.15/arch/sparc/include/asm/
Dsunbpp.h26 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
27 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
28 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
31 #define P_OCR_MEM_CLR 0x8000
32 #define P_OCR_DATA_SRC 0x4000 /* ) */
33 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
34 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
35 #define P_OCR_ACK_DSEL 0x0800 /* ) */
36 #define P_OCR_EN_DIAG 0x0400
37 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
[all …]
/linux-6.15/drivers/net/wireless/broadcom/brcm80211/include/
Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
/linux-6.15/drivers/net/ethernet/chelsio/cxgb/
Dmv88e1xxx.h7 # define BMCR_SPEED1000 0x40
11 # define ADVERTISE_PAUSE 0x400
14 # define ADVERTISE_PAUSE_ASYM 0x800
22 #define GBCR_ADV_1000HALF 0x100
23 #define GBCR_ADV_1000FULL 0x200
24 #define GBCR_PREFER_MASTER 0x400
25 #define GBCR_MANUAL_AS_MASTER 0x800
26 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
29 #define GBSR_LP_1000HALF 0x400
30 #define GBSR_LP_1000FULL 0x800
[all …]
/linux-6.15/sound/soc/codecs/
Dwm8993.h15 #define WM8993_SOFTWARE_RESET 0x00
16 #define WM8993_POWER_MANAGEMENT_1 0x01
17 #define WM8993_POWER_MANAGEMENT_2 0x02
18 #define WM8993_POWER_MANAGEMENT_3 0x03
19 #define WM8993_AUDIO_INTERFACE_1 0x04
20 #define WM8993_AUDIO_INTERFACE_2 0x05
21 #define WM8993_CLOCKING_1 0x06
22 #define WM8993_CLOCKING_2 0x07
23 #define WM8993_AUDIO_INTERFACE_3 0x08
24 #define WM8993_AUDIO_INTERFACE_4 0x09
[all …]
/linux-6.15/drivers/clk/qcom/
Dtcsrcc-sm8750.c25 .halt_reg = 0x0,
28 .enable_reg = 0x0,
29 .enable_mask = BIT(0),
38 .halt_reg = 0x1000,
41 .enable_reg = 0x1000,
42 .enable_mask = BIT(0),
55 .halt_reg = 0x2000,
58 .enable_reg = 0x2000,
59 .enable_mask = BIT(0),
72 .halt_reg = 0x3000,
[all …]
/linux-6.15/drivers/net/phy/mscc/
Dmscc.h16 RGMII_CLK_DELAY_0_2_NS = 0,
29 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
30 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
31 #define DISABLE_POLARITY_CORR_MASK 0x0010
32 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
35 #define SMI_BROADCAST_WR_EN 0x0001
40 #define ERR_CNT_MASK GENMASK(7, 0)
43 #define MAC_IF_SELECTION_MASK 0x1800
44 #define MAC_IF_SELECTION_GMII 0
48 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
[all …]
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]

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