Lines Matching +full:0 +full:x2000
16 RGMII_CLK_DELAY_0_2_NS = 0,
29 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
30 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
31 #define DISABLE_POLARITY_CORR_MASK 0x0010
32 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
35 #define SMI_BROADCAST_WR_EN 0x0001
40 #define ERR_CNT_MASK GENMASK(7, 0)
43 #define MAC_IF_SELECTION_MASK 0x1800
44 #define MAC_IF_SELECTION_GMII 0
48 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
49 #define VSC8584_MAC_IF_SELECTION_SGMII 0
52 #define FAR_END_LOOPBACK_MODE_MASK 0x0008
53 #define MEDIA_OP_MODE_MASK 0x0700
54 #define MEDIA_OP_MODE_COPPER 0
78 #define EDGE_RATE_CNTL_MASK 0x00E0
81 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
85 #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
100 #define PHY_MCB_TARGET 0x07
104 #define PHY_S6G_PLL5G_CFG0 0x06
105 #define PHY_S6G_PLL5G_CFG2 0x08
106 #define PHY_S6G_LCPLL_CFG 0x11
107 #define PHY_S6G_PLL_CFG 0x2b
108 #define PHY_S6G_COMMON_CFG 0x2c
109 #define PHY_S6G_GPC_CFG 0x2e
110 #define PHY_S6G_MISC_CFG 0x3b
111 #define PHY_MCB_S6G_CFG 0x3f
112 #define PHY_S6G_DFT_CFG2 0x3e
113 #define PHY_S6G_PLL_STATUS 0x31
114 #define PHY_S6G_IB_STATUS0 0x2f
129 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
130 #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
131 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
132 #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
133 #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
139 #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
140 #define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
141 #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
142 #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
145 #define MSCC_PHY_COMA_MODE 0x2000 /* input(1) / output(0) */
146 #define MSCC_PHY_COMA_OUTPUT 0x1000 /* value to output */
150 #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
153 #define FORCE_MDI_CROSSOVER_MASK 0x000C
154 #define FORCE_MDI_CROSSOVER_MDIX 0x000C
155 #define FORCE_MDI_CROSSOVER_MDI 0x0008
158 #define PHY_ADDR_REVERSED 0x0200
159 #define DOWNSHIFT_CNTL_MASK 0x001C
160 #define DOWNSHIFT_EN 0x0010
175 #define VSC8572_RGMII_RX_DELAY_MASK 0x000E
176 #define VSC8572_RGMII_TX_DELAY_MASK 0x0070
180 #define VSC8502_RGMII_RX_DELAY_MASK 0x0070
181 #define VSC8502_RGMII_TX_DELAY_MASK 0x0007
182 #define VSC8502_RGMII_RX_CLK_DISABLE 0x0800
192 #define SECURE_ON_ENABLE 0x8000
193 #define SECURE_ON_PASSWD_LEN_4 0x4000
205 #define MSCC_DW8051_CNTL_STATUS 0
206 #define MICRO_NSOFT_RESET 0x8000
207 #define RUN_FROM_INT_ROM 0x4000
208 #define AUTOINC_ADDR 0x2000
209 #define PATCH_RAM_CLK 0x1000
210 #define MICRO_PATCH_EN 0x0080
211 #define DW8051_CLK_EN 0x0010
212 #define MICRO_CLK_EN 0x0008
214 #define MSCC_DW8051_VLD_MASK 0xf1ff
222 #define READ_SFR 0x6000
223 #define READ_PRAM 0x4000
224 #define READ_ROM 0x2000
225 #define READ_RAM 0x0000
226 #define INT_MEM_WRITE_EN 0x1000
227 #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
228 #define INT_MEM_DATA_M 0x00ff
232 #define PROC_CMD_NCOMPLETED 0x8000
233 #define PROC_CMD_FAILED 0x4000
235 #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
236 #define PROC_CMD_QSGMII_PORT 0x0c00
237 #define PROC_CMD_RST_CONF_PORT 0x0080
238 #define PROC_CMD_RECONF_PORT 0x0000
239 #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
240 #define PROC_CMD_WRITE 0x0040
241 #define PROC_CMD_READ 0x0000
242 #define PROC_CMD_FIBER_DISABLE 0x0020
243 #define PROC_CMD_FIBER_100BASE_FX 0x0010
244 #define PROC_CMD_FIBER_1000BASE_X 0x0000
245 #define PROC_CMD_SGMII_MAC 0x0030
246 #define PROC_CMD_QSGMII_MAC 0x0020
247 #define PROC_CMD_NO_MAC_CONF 0x0000
248 #define PROC_CMD_1588_DEFAULT_INIT 0x0010
249 #define PROC_CMD_NOP 0x000f
250 #define PROC_CMD_PHY_INIT 0x000a
251 #define PROC_CMD_CRC16 0x0008
252 #define PROC_CMD_FIBER_MEDIA_CONF 0x0001
253 #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
257 #define MAC_CFG_MASK 0xc000
258 #define MAC_CFG_SGMII 0x0000
259 #define MAC_CFG_QSGMII 0x4000
260 #define MAC_CFG_RGMII 0x8000
265 #define TR_CLK_DISABLE 0x8000
272 #define TR_WRITE 0x8000
273 #define TR_ADDR(x) (0x7fff & (x))
278 * Code assumes lowest nibble is 0
280 #define PHY_ID_VSC8501 0x00070530
281 #define PHY_ID_VSC8502 0x00070630
282 #define PHY_ID_VSC8504 0x000704c0
283 #define PHY_ID_VSC8514 0x00070670
284 #define PHY_ID_VSC8530 0x00070560
285 #define PHY_ID_VSC8531 0x00070570
286 #define PHY_ID_VSC8540 0x00070760
287 #define PHY_ID_VSC8541 0x00070770
288 #define PHY_ID_VSC8552 0x000704e0
289 #define PHY_ID_VSC856X 0x000707e0
290 #define PHY_ID_VSC8572 0x000704d0
291 #define PHY_ID_VSC8574 0x000704a0
292 #define PHY_ID_VSC8575 0x000707d0
293 #define PHY_ID_VSC8582 0x000707b0
294 #define PHY_ID_VSC8584 0x000707c0
295 #define PHY_VENDOR_MSCC 0x00070400
339 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
340 #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
343 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
344 #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
346 #define VSC8584_REVB 0x0001
347 #define MSCC_DEV_REV_MASK GENMASK(3, 0)
349 #define MSCC_ROM_TRAP_SERDES_6G_CFG 0x1E48
350 #define MSCC_RAM_TRAP_SERDES_6G_CFG 0x1E4F
351 #define PATCH_VEC_ZERO_EN 0x0100
421 VSC88XX_BASE_ADDR = 0,
436 MACRO_CTRL = 0x07,
458 return 0; in vsc8584_macsec_init()
484 return 0; in vsc8584_ptp_init()
488 return 0; in vsc8584_ptp_probe_once()
492 return 0; in vsc8584_ptp_probe()