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/linux-6.8/include/linux/
Dmv643xx_eth.h15 #define MV643XX_ETH_SHARED_REGS 0x2000
16 #define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
17 #define MV643XX_ETH_BAR_4 0x2220
18 #define MV643XX_ETH_SIZE_REG_4 0x2224
19 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
21 #define MV643XX_TX_CSUM_DEFAULT_LIMIT 0
26 * Max packet size for Tx IP/Layer 4 checksum, when set to 0, default
32 #define MV643XX_ETH_PHY_ADDR_DEFAULT 0
33 #define MV643XX_ETH_PHY_ADDR(x) (0x80 | (x))
34 #define MV643XX_ETH_PHY_NONE 0xff
[all …]
/linux-6.8/Documentation/devicetree/bindings/sound/
Dqcom,wcd938x-sdw.yaml50 #size-cells = <0>;
51 reg = <0x03210000 0x2000>;
52 wcd938x_rx: codec@0,4 {
54 reg = <0 4>;
61 #size-cells = <0>;
62 reg = <0x03230000 0x2000>;
63 wcd938x_tx: codec@0,3 {
65 reg = <0 3>;
/linux-6.8/arch/arm/boot/dts/renesas/
Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/linux-6.8/arch/arm/boot/dts/samsung/
Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/dma/
Dfsl,mxs-dma.yaml60 reg = <0x80004000 0x2000>;
64 87 86 0 0>;
71 reg = <0x80024000 0x2000>;
72 interrupts = <78 79 66 0
/linux-6.8/arch/arm/mach-omap2/
Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
/linux-6.8/include/linux/mfd/wm831x/
Dwatchdog.h15 * R16388 (0x4004) - Watchdog
17 #define WM831X_WDOG_ENA 0x8000 /* WDOG_ENA */
18 #define WM831X_WDOG_ENA_MASK 0x8000 /* WDOG_ENA */
21 #define WM831X_WDOG_DEBUG 0x4000 /* WDOG_DEBUG */
22 #define WM831X_WDOG_DEBUG_MASK 0x4000 /* WDOG_DEBUG */
25 #define WM831X_WDOG_RST_SRC 0x2000 /* WDOG_RST_SRC */
26 #define WM831X_WDOG_RST_SRC_MASK 0x2000 /* WDOG_RST_SRC */
29 #define WM831X_WDOG_SLPENA 0x1000 /* WDOG_SLPENA */
30 #define WM831X_WDOG_SLPENA_MASK 0x1000 /* WDOG_SLPENA */
33 #define WM831X_WDOG_RESET 0x0800 /* WDOG_RESET */
[all …]
/linux-6.8/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux-6.8/Documentation/devicetree/bindings/mfd/
Dmxs-lradc.txt27 reg = <0x80050000 0x2000>;
39 reg = <0x80050000 0x2000>;
/linux-6.8/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-soc-glue-debug.yaml45 "^efuse@[0-9a-f]+$":
59 reg = <0x5f900000 0x2000>;
62 ranges = <0 0x5f900000 0x2000>;
66 reg = <0x100 0x28>;
/linux-6.8/Documentation/devicetree/bindings/pci/
Daxis,artpec6-pcie.txt28 reg = <0xf8050000 0x2000
29 0xf8040000 0x1000
30 0xc0000000 0x2000>;
36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
40 bus-range = <0x00 0xff>;
44 interrupt-map-mask = <0 0 0 0x7>;
45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.8/drivers/net/ethernet/intel/e1000e/
D80003es2lan.h7 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
8 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
9 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
10 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
12 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
13 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
14 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
16 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
17 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
18 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux-6.8/include/uapi/linux/
Dmdio.h76 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
79 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
89 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
90 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
91 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
92 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
93 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
94 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
100 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
104 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
[all …]
/linux-6.8/sound/soc/codecs/
Dwm5100.h26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
45 #define WM5100_FLL_SRC_AIF3BCLK 0xa
50 #define WM5100_SOFTWARE_RESET 0x00
[all …]
Dwm8995.h18 #define WM8995_SOFTWARE_RESET 0x00
19 #define WM8995_POWER_MANAGEMENT_1 0x01
20 #define WM8995_POWER_MANAGEMENT_2 0x02
21 #define WM8995_POWER_MANAGEMENT_3 0x03
22 #define WM8995_POWER_MANAGEMENT_4 0x04
23 #define WM8995_POWER_MANAGEMENT_5 0x05
24 #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
25 #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
26 #define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
27 #define WM8995_DAC1_LEFT_VOLUME 0x18
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Dingenic,mac.yaml22 - ingenic,x2000-mac
66 reg = <0x134b0000 0x2000>;
/linux-6.8/drivers/media/usb/gspca/
Dsunplus.c29 #define BRIDGE_SPCA504 0
113 /* {0xa0, 0x0000, 0x0503}, * capture mode */
114 {0x00, 0x0000, 0x2000},
115 {0x00, 0x0013, 0x2301},
116 {0x00, 0x0003, 0x2000},
117 {0x00, 0x0001, 0x21ac},
118 {0x00, 0x0001, 0x21a6},
119 {0x00, 0x0000, 0x21a7}, /* brightness */
120 {0x00, 0x0020, 0x21a8}, /* contrast */
121 {0x00, 0x0001, 0x21ac}, /* sat/hue */
[all …]
/linux-6.8/arch/arm64/boot/dts/arm/
Drtsm_ve-aemv8a.dts15 /memreserve/ 0x80000000 0x00010000;
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0x0 0x0>;
44 cpu-release-addr = <0x0 0x8000fff8>;
50 reg = <0x0 0x1>;
52 cpu-release-addr = <0x0 0x8000fff8>;
58 reg = <0x0 0x2>;
60 cpu-release-addr = <0x0 0x8000fff8>;
66 reg = <0x0 0x3>;
[all …]
/linux-6.8/arch/sh/include/asm/
Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/linux-6.8/arch/powerpc/boot/dts/
Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x2000000>;
52 reg = <0xfff00100 0x40>;
[all …]
/linux-6.8/include/linux/mfd/wm8994/
Dgpio.h15 #define WM8994_GP_FN_PIN_SPECIFIC 0
39 #define WM8994_GPN_DIR 0x8000 /* GPN_DIR */
40 #define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */
43 #define WM8994_GPN_PU 0x4000 /* GPN_PU */
44 #define WM8994_GPN_PU_MASK 0x4000 /* GPN_PU */
47 #define WM8994_GPN_PD 0x2000 /* GPN_PD */
48 #define WM8994_GPN_PD_MASK 0x2000 /* GPN_PD */
51 #define WM8994_GPN_POL 0x0400 /* GPN_POL */
52 #define WM8994_GPN_POL_MASK 0x0400 /* GPN_POL */
55 #define WM8994_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/linux-6.8/drivers/net/phy/
Dmicrochip_t1s.c14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN865X_REVB0 0x0007C1B3
17 #define LAN867X_REG_STS2 0x0019
21 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
22 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
23 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
24 #define LAN865X_REG_STS2 0x0019
30 * RMW 0x1F 0x00D0 0x0002 0x0E03
31 * RMW 0x1F 0x00D1 0x0000 0x0300
32 * RMW 0x1F 0x0084 0x3380 0xFFC0
[all …]

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