Lines Matching +full:0 +full:x2000

7 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00
8 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02
9 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10
10 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F
12 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
13 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800
14 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010
16 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
17 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000
18 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000
20 #define E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C
21 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004
23 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00	/* Gig Carry Extend Padding */
24 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000
26 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8
27 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9
29 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
30 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002	/* 1=Reversal Dis */
31 #define GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060
32 #define GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000	/* 00=Manual MDI */
33 #define GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020	/* 01=Manual MDIX */
34 #define GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060	/* 11=Auto crossover */
36 /* PHY Specific Control Register 2 (Page 0, Register 26) */
37 #define GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000	/* 1=Reverse Auto-Neg */
41 #define GG82563_MSCR_TX_CLK_MASK		0x0007
42 #define GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004
43 #define GG82563_MSCR_TX_CLK_100MBPS_25		0x0005
44 #define GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007
46 #define GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010	/* 1=Assert */
49  * 0 = <50M
55 #define GG82563_DSPD_CABLE_LENGTH		0x0007
58 #define GG82563_KMCR_PASS_FALSE_CARRIER		0x0800
61 #define GG82563_MAX_KMRN_RETRY			0x5
65 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001
68 #define GG82563_ICR_DIS_PADDING			0x0010	/* Disable Padding */