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/linux/drivers/clk/samsung/
H A Dclk-exynos990.c26 /* Register Offset definitions for CMU_TOP (0x1a330000) */
27 #define PLL_LOCKTIME_PLL_G3D 0x0000
28 #define PLL_LOCKTIME_PLL_MMC 0x0004
29 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
30 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
31 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
32 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
33 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
34 #define PLL_CON0_PLL_G3D 0x0100
35 #define PLL_CON3_PLL_G3D 0x010c
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-ingenic.c24 #define MACPHYC_TXCLK_SEL_OUTPUT 0x1
25 #define MACPHYC_TXCLK_SEL_INPUT 0x0
27 #define MACPHYC_MODE_SEL_RMII 0x0
29 #define MACPHYC_TX_SEL_ORIGIN 0x0
30 #define MACPHYC_TX_SEL_DELAY 0x1
33 #define MACPHYC_RX_SEL_ORIGIN 0x0
34 #define MACPHYC_RX_SEL_DELAY 0x1
37 #define MACPHYC_PHY_INFT_MASK GENMASK(2, 0)
38 #define MACPHYC_PHY_INFT_RMII 0x4
39 #define MACPHYC_PHY_INFT_RGMII 0x1
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
[all …]
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
/linux/drivers/phy/socionext/
H A Dphy-uniphier-pcie.c22 #define PCL_PHY_CLKCTRL 0x0000
26 #define PCL_PHY_TEST_I 0x2000
29 #define TESTI_WR_EN BIT(0)
32 #define PCL_PHY_TEST_O 0x2004
33 #define TESTO_DAT_MASK GENMASK(7, 0)
35 #define PCL_PHY_RESET 0x200c
37 #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
40 #define SG_USBPCIESEL 0x590
41 #define SG_USBPCIESEL_PCIE BIT(0)
44 #define SC_US3SRCSEL 0x2244
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
41 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
62 {0, 0, 0},
64 {0x40, 0x40, 0x40},
66 {0x200, 0x40, 0x200},
68 {0x1f4, 0x40, 0x1f4},
70 {0x1a2, 0x20, 0x1a2},
72 {0xff, 0xff, 0},
82 { 0x2000, 0, 0, 0,
83 0, 0x2000, 0, 0,
[all …]
/linux/arch/powerpc/kernel/
H A Dhead_book3s_32.S41 li RA,0; \
44 lwz RA,(n*16)+0(reg); \
73 * 0, running with virtual == physical mapping.
78 * from 0x380000 - 0x400000, which is mapped in already.
82 * r3: 'BooX' (0x426f6f58)
84 * r5: 0
91 * r4: initrd_start or if no initrd then 0
92 * r5: initrd_end - unused if r4 is 0
108 cmpwi 0,r5,0
114 0: mflr r8 /* r8 = runtime addr here */
[all …]
/linux/sound/soc/amd/acp/
H A Dacp-platform.c116 stream->reg_offset = 0x02000000; in config_pte_for_stream()
127 writel(0x01, chip->base + ACPAXI2AXI_ATU_CTRL); in config_pte_for_stream()
147 val = 0x0; in config_acp_dma()
149 val = 0x1000; in config_acp_dma()
153 val = 0x2000; in config_acp_dma()
155 val = 0x3000; in config_acp_dma()
159 val = 0x4000; in config_acp_dma()
161 val = 0x5000; in config_acp_dma()
164 val = 0x6000; in config_acp_dma()
176 for (page_idx = 0; page_idx < num_pages; page_idx++) { in config_acp_dma()
[all …]
/linux/drivers/net/ethernet/rdc/
H A Dr6040.c50 #define MCR0 0x00 /* Control register 0 */
51 #define MCR0_RCVEN 0x0002 /* Receive enable */
52 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
54 #define MCR0_XMTEN 0x1000 /* Transmission enable */
55 #define MCR0_FD 0x8000 /* Full/Half duplex */
56 #define MCR1 0x04 /* Control register 1 */
57 #define MAC_RST 0x0001 /* Reset the MAC */
58 #define MBCR 0x08 /* Bus control */
59 #define MT_ICR 0x0C /* TX interrupt control */
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dphy.c33 0x4D, 0x4C, 0x4B, 0x4A,
34 0x4A, 0x49, 0x48, 0x47,
35 0x47, 0x46, 0x45, 0x45,
36 0x44, 0x43, 0x42, 0x42,
37 0x41, 0x40, 0x3F, 0x3E,
38 0x3D, 0x3C, 0x3B, 0x3A,
39 0x39, 0x38, 0x37, 0x36,
40 0x35, 0x34, 0x32, 0x31,
41 0x30, 0x2F, 0x2D, 0x2C,
42 0x2B, 0x29, 0x28, 0x26,
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77951.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]
/linux/drivers/net/ethernet/microchip/
H A Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpcie_vdec0_brdg_ctrl_masks.h24 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
[all …]
H A Ddcore0_vdec0_brdg_ctrl_masks.h24 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
[all …]
/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_adminq_cmd.h15 #define IAVF_FW_API_VERSION_MAJOR 0x0001
16 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005
17 #define IAVF_FW_API_VERSION_MINOR_X710 0x0008
24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 iavf_aqc_opc_get_version = 0x0001,
30 iavf_aqc_opc_driver_version = 0x0002,
31 iavf_aqc_opc_queue_shutdown = 0x0003,
32 iavf_aqc_opc_set_pf_context = 0x0004,
35 iavf_aqc_opc_request_resource = 0x0008,
36 iavf_aqc_opc_release_resource = 0x0009,
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.h10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
28 #define HCLGE_COMM_TYPE_CRQ 0
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
[all …]
/linux/drivers/scsi/
H A Daha152x.h16 #define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */
17 #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
18 #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
19 #define SCSISIG (HOSTIOPORT0+0x03) /* SCSI signal in/out */
20 #define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */
21 #define SELID (HOSTIOPORT0+0x05) /* selection/reselection ID */
23 #define SCSIDAT (HOSTIOPORT0+0x06) /* SCSI latched data */
24 #define SCSIBUS (HOSTIOPORT0+0x07) /* SCSI data bus */
25 #define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */
26 #define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dbamboo.dts21 dcr-parent = <&{/cpus/cpu@0}>;
34 #size-cells = <0>;
36 cpu@0 {
39 reg = <0x00000000>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_regs.h19 #define LDDCKPAT1R 0x400
20 #define LDDCKPAT2R 0x404
21 #define LDDCKR 0x410
22 #define LDDCKR_ICKSEL_BUS (0 << 16)
28 #define LDDCKSTPR 0x414
30 #define LDDCKSTPR_DCKSTP (1 << 0)
31 #define LDMT1R 0x418
40 #define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
41 #define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
42 #define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpc52xx_psc.h35 #define MPC52xx_PSC_SR_UNEX_RX 0x0001
36 #define MPC52xx_PSC_SR_DATA_VAL 0x0002
37 #define MPC52xx_PSC_SR_DATA_OVR 0x0004
38 #define MPC52xx_PSC_SR_CMDSEND 0x0008
39 #define MPC52xx_PSC_SR_CDE 0x0080
40 #define MPC52xx_PSC_SR_RXRDY 0x0100
41 #define MPC52xx_PSC_SR_RXFULL 0x0200
42 #define MPC52xx_PSC_SR_TXRDY 0x0400
43 #define MPC52xx_PSC_SR_TXEMP 0x0800
44 #define MPC52xx_PSC_SR_OE 0x1000
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_hw.h40 #define CSR_RING_ID 0x0008
44 #define CSR_RING_ID_BUF 0x000c
45 #define CSR_PBM_COAL 0x0014
46 #define CSR_PBM_CTICK0 0x0018
47 #define CSR_PBM_CTICK1 0x001c
48 #define CSR_PBM_CTICK2 0x0020
49 #define CSR_PBM_CTICK3 0x0024
50 #define CSR_THRESHOLD0_SET1 0x0030
51 #define CSR_THRESHOLD1_SET1 0x0034
52 #define CSR_RING_NE_INT_MODE 0x017c
[all …]

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