Lines Matching +full:0 +full:x2000
35 #define MPC52xx_PSC_SR_UNEX_RX 0x0001
36 #define MPC52xx_PSC_SR_DATA_VAL 0x0002
37 #define MPC52xx_PSC_SR_DATA_OVR 0x0004
38 #define MPC52xx_PSC_SR_CMDSEND 0x0008
39 #define MPC52xx_PSC_SR_CDE 0x0080
40 #define MPC52xx_PSC_SR_RXRDY 0x0100
41 #define MPC52xx_PSC_SR_RXFULL 0x0200
42 #define MPC52xx_PSC_SR_TXRDY 0x0400
43 #define MPC52xx_PSC_SR_TXEMP 0x0800
44 #define MPC52xx_PSC_SR_OE 0x1000
45 #define MPC52xx_PSC_SR_PE 0x2000
46 #define MPC52xx_PSC_SR_FE 0x4000
47 #define MPC52xx_PSC_SR_RB 0x8000
50 #define MPC52xx_PSC_RX_ENABLE 0x0001
51 #define MPC52xx_PSC_RX_DISABLE 0x0002
52 #define MPC52xx_PSC_TX_ENABLE 0x0004
53 #define MPC52xx_PSC_TX_DISABLE 0x0008
54 #define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
55 #define MPC52xx_PSC_RST_RX 0x0020
56 #define MPC52xx_PSC_RST_TX 0x0030
57 #define MPC52xx_PSC_RST_ERR_STAT 0x0040
58 #define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
59 #define MPC52xx_PSC_START_BRK 0x0060
60 #define MPC52xx_PSC_STOP_BRK 0x0070
63 #define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
64 #define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
65 #define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
66 #define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
67 #define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
68 #define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
69 #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
72 #define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
73 #define MPC52xx_PSC_IMR_DATA_VALID 0x0002
74 #define MPC52xx_PSC_IMR_DATA_OVR 0x0004
75 #define MPC52xx_PSC_IMR_CMD_SEND 0x0008
76 #define MPC52xx_PSC_IMR_ERROR 0x0040
77 #define MPC52xx_PSC_IMR_DEOF 0x0080
78 #define MPC52xx_PSC_IMR_TXRDY 0x0100
79 #define MPC52xx_PSC_IMR_RXRDY 0x0200
80 #define MPC52xx_PSC_IMR_DB 0x0400
81 #define MPC52xx_PSC_IMR_TXEMP 0x0800
82 #define MPC52xx_PSC_IMR_ORERR 0x1000
83 #define MPC52xx_PSC_IMR_IPC 0x8000
86 #define MPC52xx_PSC_CTS 0x01
87 #define MPC52xx_PSC_DCD 0x02
88 #define MPC52xx_PSC_D_CTS 0x10
89 #define MPC52xx_PSC_D_DCD 0x20
92 #define MPC52xx_PSC_IEC_CTS 0x01
93 #define MPC52xx_PSC_IEC_DCD 0x02
96 #define MPC52xx_PSC_OP_RTS 0x01
97 #define MPC52xx_PSC_OP_RES 0x02
100 #define MPC52xx_PSC_MODE_5_BITS 0x00
101 #define MPC52xx_PSC_MODE_6_BITS 0x01
102 #define MPC52xx_PSC_MODE_7_BITS 0x02
103 #define MPC52xx_PSC_MODE_8_BITS 0x03
104 #define MPC52xx_PSC_MODE_BITS_MASK 0x03
105 #define MPC52xx_PSC_MODE_PAREVEN 0x00
106 #define MPC52xx_PSC_MODE_PARODD 0x04
107 #define MPC52xx_PSC_MODE_PARFORCE 0x08
108 #define MPC52xx_PSC_MODE_PARNONE 0x10
109 #define MPC52xx_PSC_MODE_ERR 0x20
110 #define MPC52xx_PSC_MODE_FFULL 0x40
111 #define MPC52xx_PSC_MODE_RXRTS 0x80
113 #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
114 #define MPC52xx_PSC_MODE_ONE_STOP 0x07
115 #define MPC52xx_PSC_MODE_TWO_STOP 0x0f
116 #define MPC52xx_PSC_MODE_TXCTS 0x10
118 #define MPC52xx_PSC_RFNUM_MASK 0x01ff
122 #define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
123 #define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
124 #define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
125 #define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
126 #define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
127 #define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
128 #define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
129 #define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
130 #define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
131 #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
132 #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
133 #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
134 #define MPC52xx_PSC_SICR_ACRB (0x8 << 24)
154 u8 mode; /* PSC + 0x00 */
158 union { /* PSC + 0x04 */
165 u8 command; /* PSC + 0x08 */
167 union { /* PSC + 0x0c */
175 union { /* PSC + 0x10 */
182 union { /* PSC + 0x14 */
189 u8 ctur; /* PSC + 0x18 */
191 u8 ctlr; /* PSC + 0x1c */
195 u32 ccr; /* PSC + 0x20 */
196 u32 ac97_slots; /* PSC + 0x24 */
197 u32 ac97_cmd; /* PSC + 0x28 */
198 u32 ac97_data; /* PSC + 0x2c */
199 u8 ivr; /* PSC + 0x30 */
201 u8 ip; /* PSC + 0x34 */
203 u8 op1; /* PSC + 0x38 */
205 u8 op0; /* PSC + 0x3c */
207 u32 sicr; /* PSC + 0x40 */
208 u8 ircr1; /* PSC + 0x44 */
210 u8 ircr2; /* PSC + 0x44 */
212 u8 irsdr; /* PSC + 0x4c */
214 u8 irmdr; /* PSC + 0x50 */
216 u8 irfdr; /* PSC + 0x54 */
221 u16 rfnum; /* PSC + 0x58 */
223 u16 tfnum; /* PSC + 0x5c */
225 u32 rfdata; /* PSC + 0x60 */
226 u16 rfstat; /* PSC + 0x64 */
228 u8 rfcntl; /* PSC + 0x68 */
230 u16 rfalarm; /* PSC + 0x6e */
232 u16 rfrptr; /* PSC + 0x72 */
234 u16 rfwptr; /* PSC + 0x76 */
236 u16 rflrfptr; /* PSC + 0x7a */
238 u16 rflwfptr; /* PSC + 0x7e */
239 u32 tfdata; /* PSC + 0x80 */
240 u16 tfstat; /* PSC + 0x84 */
242 u8 tfcntl; /* PSC + 0x88 */
244 u16 tfalarm; /* PSC + 0x8e */
246 u16 tfrptr; /* PSC + 0x92 */
248 u16 tfwptr; /* PSC + 0x96 */
250 u16 tflrfptr; /* PSC + 0x9a */
252 u16 tflwfptr; /* PSC + 0x9e */
255 #define MPC512x_PSC_FIFO_EOF 0x100
256 #define MPC512x_PSC_FIFO_RESET_SLICE 0x80
257 #define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
258 #define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
260 #define MPC512x_PSC_FIFO_EMPTY 0x1
261 #define MPC512x_PSC_FIFO_FULL 0x2
262 #define MPC512x_PSC_FIFO_ALARM 0x4
263 #define MPC512x_PSC_FIFO_URERR 0x8
267 u32 txcmd; /* PSC + 0x80 */
268 u32 txalarm; /* PSC + 0x84 */
269 u32 txsr; /* PSC + 0x88 */
270 u32 txisr; /* PSC + 0x8c */
271 u32 tximr; /* PSC + 0x90 */
272 u32 txcnt; /* PSC + 0x94 */
273 u32 txptr; /* PSC + 0x98 */
274 u32 txsz; /* PSC + 0x9c */
280 } txdata; /* PSC + 0xbc */
284 u32 rxcmd; /* PSC + 0xc0 */
285 u32 rxalarm; /* PSC + 0xc4 */
286 u32 rxsr; /* PSC + 0xc8 */
287 u32 rxisr; /* PSC + 0xcc */
288 u32 rximr; /* PSC + 0xd0 */
289 u32 rxcnt; /* PSC + 0xd4 */
290 u32 rxptr; /* PSC + 0xd8 */
291 u32 rxsz; /* PSC + 0xdc */
297 } rxdata; /* PSC + 0xfc */
304 u8 mr1; /* PSC + 0x00 */
306 u8 mr2; /* PSC + 0x04 */
309 u16 status; /* PSC + 0x08 */
311 u8 clock_select; /* PSC + 0x0c */
314 u8 command; /* PSC + 0x10 */
316 union { /* PSC + 0x14 */
322 u8 ipcr; /* PSC + 0x18 */
324 u8 acr; /* PSC + 0x1c */
328 u16 isr; /* PSC + 0x20 */
330 u16 imr; /* PSC + 0x24 */
333 u8 ctur; /* PSC + 0x28 */
335 u8 ctlr; /* PSC + 0x2c */
337 u32 ccr; /* PSC + 0x30 */
338 u32 ac97slots; /* PSC + 0x34 */
339 u32 ac97cmd; /* PSC + 0x38 */
340 u32 ac97data; /* PSC + 0x3c */
342 u8 ip; /* PSC + 0x44 */
344 u8 op1; /* PSC + 0x48 */
346 u8 op0; /* PSC + 0x4c */
348 u32 sicr; /* PSC + 0x50 */