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/qemu/target/ppc/translate/
H A Dfp-ops.c.inc2 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
4 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
5 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
6 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
7 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
8 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
11 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
12 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
[all …]
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
/qemu/disas/
H A Dalpha.c65 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
66 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
67 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
68 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
69 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
70 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
71 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
76 #define AXP_OP(i) (((i) >> 26) & 0x3F)
79 #define AXP_NOPS 0x40
122 if ((o->flags & AXP_OPERAND_SIGNED) != 0
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]
/qemu/hw/display/
H A Dpl110_template.h16 #if ORDER == 0
36 #define FN_8(y) FN_4(0, y) FN_4(4, y)
42 while (width > 0) { in glue()
53 FN_8(0) in glue()
55 FN_8(0) in glue()
70 while (width > 0) { in glue()
78 FN_4(0, 24) in glue()
79 FN_4(0, 16) in glue()
80 FN_4(0, 8) in glue()
81 FN_4(0, 0) in glue()
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_sar.S11 test_sar \prefix, 0
15 test_sar \prefix, 0x1f
16 test_sar \prefix, 0x20
17 test_sar \prefix, 0x3f
18 test_sar \prefix, 0x40
19 test_sar \prefix, 0xfffffffe
29 movi a2, \imm & 0x3f
44 movi a2, \imm & 0x1f
59 movi a2, 32 - (\imm & 0x1f)
74 movi a2, (\imm & 0x3) << 3
[all …]
H A Dtest_shift.S26 test_shift_sd \prefix, \v, 0
39 movi a3, ((\v) << (\imm)) & 0xffffffff
44 tests_imm_shift slli, 0xa3c51249
56 movi a3, (((\v) >> (\imm)) & 0xffffffff) | \
57 ~((((\v) & 0x80000000) >> ((\imm) - 1)) - 1)
65 tests_imm_shift srai, 0x49a3c512
66 tests_imm_shift srai, 0xa3c51249
77 movi a3, (((\v) >> (\imm)) & 0xffffffff)
82 tests_imm_shift srli, 0x49a3c512
83 tests_imm_shift srli, 0xa3c51249
[all …]
H A Dtest_break.S12 set_vector debug_vector, 0
14 _break 0, 0
19 _break 0, 0
23 movi a3, 0x1f
25 movi a3, 0x10 | debug_level
31 movi a3, 0x8
36 set_vector debug_vector, 0
38 _break.n 0
43 _break.n 0
47 movi a3, 0x1f
[all …]
/qemu/target/ppc/
H A Dtranslate.c46 #define CPU_SINGLE_STEP 0x1
47 #define CPU_BRANCH_STEP 0x2
55 # define LOG_DISAS(...) do { } while (0)
93 for (i = 0; i < 8; i++) { in ppc_translate_init()
101 for (i = 0; i < 32; i++) { in ppc_translate_init()
226 # define NARROW_MODE(C) 0
230 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
363 target_ulong dbsr = 0; in gen_debug_exception()
410 #if 0 in spr_noaccess()
411 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); in spr_noaccess()
[all …]
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_shift.c.inc9 tcg_gen_andi_tl(t0, src2, 0x1f);
16 tcg_gen_andi_tl(t0, src2, 0x1f);
23 tcg_gen_andi_tl(t0, src2, 0x1f);
30 tcg_gen_andi_tl(t0, src2, 0x3f);
37 tcg_gen_andi_tl(t0, src2, 0x3f);
44 tcg_gen_andi_tl(t0, src2, 0x3f);
54 tcg_gen_andi_tl(t0, src2, 0x1f);
66 tcg_gen_andi_tl(t0, src2, 0x3f);
/qemu/hw/net/fsl_etsec/
H A Dmiim.c38 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_read_cycle()
40 addr = etsec->regs[MIIMADD].value & 0x1F; in miim_read_cycle()
53 value = 0x0; in miim_read_cycle()
58 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_read_cycle()
70 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_write_cycle()
72 addr = etsec->regs[MIIMADD].value & 0x1F; in miim_write_cycle()
73 value = etsec->regs[MIIMCON].value & 0xffff; in miim_write_cycle()
76 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_write_cycle()
107 reg->value = value & 0xffff; in etsec_write_miim()
/qemu/hw/rtc/
H A Daspeed_rtc.c18 #define COUNTER1 (0x00 / 4)
19 #define COUNTER2 (0x04 / 4)
20 #define ALARM (0x08 / 4)
21 #define CONTROL (0x10 / 4)
22 #define ALARM_STATUS (0x14 / 4)
25 #define RTC_ENABLED BIT(0)
34 tm.tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_calc_offset()
35 tm.tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_calc_offset()
36 tm.tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_calc_offset()
37 tm.tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_calc_offset()
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_extr_rs_w.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 result = 0x7FFFFFFF; in main()
15 "extr_rs.w %0, $ac1, 0x03\n\t" in main()
20 dsp = (dsp >> 23) & 0x01; in main()
25 dsp = 0; in main()
27 ("wrdsp %0\n\t" in main()
32 ach = 0x01; in main()
33 acl = 0xB4CB; in main()
34 result = 0x10000B4D; in main()
[all …]
H A Dtest_dsp_r1_extp.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 dsp = 0x07; in main()
12 result = 0x000C; in main()
15 ("wrdsp %1, 0x01\n\t" in main()
18 "extp %0, $ac1, 0x03\n\t" in main()
23 dsp = (dsp >> 14) & 0x01; in main()
24 assert(dsp == 0); in main()
27 ach = 0x05; in main()
28 acl = 0xB4CB; in main()
[all …]
H A Dtest_dsp_r1_extr_r_w.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 result = 0xA0001699; in main()
15 "extr_r.w %0, $ac1, 0x03\n\t" in main()
20 dsp = (dsp >> 23) & 0x01; in main()
25 dsp = 0; in main()
27 ("wrdsp %0\n\t" in main()
32 ach = 0x01; in main()
33 acl = 0xB4CB; in main()
34 result = 0x10000B4D; in main()
[all …]
H A Dtest_dsp_r1_extr_w.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 result = 0xA0001699; in main()
15 "extr.w %0, $ac1, 0x03\n\t" in main()
20 dsp = (dsp >> 23) & 0x01; in main()
25 dsp = 0; in main()
27 ("wrdsp %0\n\t" in main()
32 ach = 0x01; in main()
33 acl = 0xB4CB; in main()
34 result = 0x10000B4C; in main()
[all …]
/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_input.h18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
/qemu/tests/tcg/x86_64/
H A Dtest-2413.c11 "testb $0x20, %%cl\n\t" in test()
24 for (c = 0; c < 64; c++) { in main()
26 assert(a == (c & 0x20 ? 0 : 1u << (c & 0x1f))); in main()
27 assert(d == (c & 0x20 ? 1u << (c & 0x1f) : 0)); in main()
29 return 0; in main()
/qemu/pc-bios/keymaps/
H A Dsl3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
/qemu/target/mips/tcg/
H A Dmips16e_translate.c.inc14 M16_OPC_ADDIUSP = 0x00,
15 M16_OPC_ADDIUPC = 0x01,
16 M16_OPC_B = 0x02,
17 M16_OPC_JAL = 0x03,
18 M16_OPC_BEQZ = 0x04,
19 M16_OPC_BNEQZ = 0x05,
20 M16_OPC_SHIFT = 0x06,
21 M16_OPC_LD = 0x07,
22 M16_OPC_RRIA = 0x08,
23 M16_OPC_ADDIU8 = 0x09,
[all …]
H A Dmicromips_translate.c.inc25 POOL32A = 0x00,
26 POOL16A = 0x01,
27 LBU16 = 0x02,
28 MOVE16 = 0x03,
29 ADDI32 = 0x04,
30 R6_LUI = 0x04,
31 AUI = 0x04,
32 LBU32 = 0x05,
33 SB32 = 0x06,
34 LB32 = 0x07,
[all …]
/qemu/tests/unit/
H A Dtest-crypto-ivgen.c40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
51 .iv = (const uint8_t *)"\x4c\x3d\x2e\x1f\x00\x00\x00\x00"
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
78 .iv = (const uint8_t *)"\x4c\x3d\x2e\x1f\x00\x00\x00\x00"
85 .sector = 0x1f2e3d4c5b6a7988ULL,
87 .iv = (const uint8_t *)"\x88\x79\x6a\x5b\x4c\x3d\x2e\x1f"
94 .sector = 0x1,
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
38 "\xd1\x26\x6a\x1c\x83\xcc\xf4\x1f\x53\x42\x72\x1f\x62\x57\x0a\xc4"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
72 "\x7f\x30\x25\x03\xd4\x3a\xff\xa2\xe8\xd6\xb5\x1f\x4f\x36\x64\x61"
91 "\xec\x45\x1f\xbf\x25\x4c\x30\x26\x76\x4f\x09\x13\x83\xef\x35\x73"
96 "\x1f\x84\x87\xf4\x92\x8a\x6c\x44\x20\xaa\x8d\xd8\x50\xde\x45\x74"
122 "\x77\x4e\x73\xad\xd9\x24\xa8\x85\x8b\x26\x75\xd7\x1f\x66\x41\x41"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
169 "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */
[all …]
/qemu/hw/misc/
H A Daxp2xx.c43 #define NR_REGS (0xff)
62 #define AXP209_CHIP_VERSION_ID (0x01)
63 #define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16)
68 memset(s->regs, 0, NR_REGS); in axp209_reset_enter()
69 s->ptr = 0; in axp209_reset_enter()
70 s->count = 0; in axp209_reset_enter()
72 s->regs[0x03] = AXP209_CHIP_VERSION_ID; in axp209_reset_enter()
73 s->regs[0x23] = AXP209_DC_DC2_OUT_V_CTRL_RESET; in axp209_reset_enter()
75 s->regs[0x30] = 0x60; in axp209_reset_enter()
76 s->regs[0x32] = 0x46; in axp209_reset_enter()
[all …]
/qemu/pc-bios/s390-ccw/
H A Dscsi.h20 #define CDB_STATUS_GOOD 0
21 #define CDB_STATUS_CHECK_CONDITION 0x02U
22 #define CDB_STATUS_VALID(status) (((status) & ~0x3eU) == 0)
24 #define SCSI_SENSE_CODE_MASK 0x7fU
25 #define SCSI_SENSE_KEY_MASK 0x0fU
26 #define SCSI_SENSE_KEY_NO_SENSE 0
30 #define SCSI_INQUIRY_STANDARD 0x00U
31 #define SCSI_INQUIRY_EVPD 0x01U
34 #define SCSI_INQUIRY_STANDARD_NONE 0x00U
35 #define SCSI_INQUIRY_EVPD_SUPPORTED_PAGES 0x00U
[all …]

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