Lines Matching +full:0 +full:x1f

18 #define COUNTER1        (0x00 / 4)
19 #define COUNTER2        (0x04 / 4)
20 #define ALARM           (0x08 / 4)
21 #define CONTROL         (0x10 / 4)
22 #define ALARM_STATUS    (0x14 / 4)
25 #define RTC_ENABLED     BIT(0)
34     tm.tm_mday = (reg1 >> 24) & 0x1f;  in aspeed_rtc_calc_offset()
35     tm.tm_hour = (reg1 >> 16) & 0x1f;  in aspeed_rtc_calc_offset()
36     tm.tm_min = (reg1 >> 8) & 0x3f;  in aspeed_rtc_calc_offset()
37     tm.tm_sec = (reg1 >> 0) & 0x3f;  in aspeed_rtc_calc_offset()
39     cent = (reg2 >> 16) & 0x1f;  in aspeed_rtc_calc_offset()
40     year = (reg2 >> 8) & 0x7f;  in aspeed_rtc_calc_offset()
41     tm.tm_mon = ((reg2 >>  0) & 0x0f) - 1;  in aspeed_rtc_calc_offset()
61         return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) |  in aspeed_rtc_get_counter()
62             ((now.tm_mon + 1) & 0xf);  in aspeed_rtc_get_counter()
88         qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);  in aspeed_rtc_read()
89         return 0;  in aspeed_rtc_read()
117         qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);  in aspeed_rtc_write()
127     rtc->offset = 0;  in aspeed_rtc_reset()
128     memset(rtc->reg, 0, sizeof(rtc->reg));  in aspeed_rtc_reset()
141         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
155                           "aspeed-rtc", 0x18ULL);  in aspeed_rtc_realize()