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/linux-5.10/lib/raid6/
Dneon.uc43 * The MASK() operation returns 0xFF in any byte for which the high
44 * bit is 1, 0x00 for any byte for which the high bit is 0.
63 const unative_t x1d = vdupq_n_u8(0x1d);
69 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
71 for ( z = z0-1 ; z >= 0 ; z-- ) {
77 w2$$ = vandq_u8(w2$$, x1d);
94 const unative_t x1d = vdupq_n_u8(0x1d);
100 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
111 w2$$ = vandq_u8(w2$$, x1d);
120 w2$$ = PMUL(w2$$, x1d);
[all …]
/linux-5.10/crypto/
Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
199 "\xDF\x8E\x8A\xE5\x9D\x73\x3D\x9F\x33\xB3\x01\x62\x4A\xFD\x1D\x51"
209 "\x5e\x32\x39\x6d\xc1\x1d\x7d\x50\x3b\x9f\x7a\xad\xf0\x2e\x25\x53"
216 "\x30\x82\x01\x1D" /* sequence of 285 bytes */
226 "\x7F\xE2\x53\x72\x98\xCA\x2A\x8F\x59\x46\xF8\xE5\xFD\x09\x1D\xBD"
265 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
292 "\xA6\xFF\x46\x83\x97\xDE\xE9\xE2\x17\x03\x06\x14\xE2\xD7\xB1\x1D"
296 "\xA7\x1D\xD9\x1E\x06\xCD\xE8\xBA\x2C\x8C\x69\x32\xEA\xBE\x60\x71"
329 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
[all …]
/linux-5.10/drivers/media/dvb-frontends/
Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
Ditd1000.c31 } while (0)
35 } while (0)
39 } while (0)
46 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 in itd1000_write_regs()
56 buf[0] = reg; in itd1000_write_regs()
59 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ in itd1000_write_regs()
65 return 0; in itd1000_write_regs()
72 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, in itd1000_read_reg()
77 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); in itd1000_read_reg()
100 { 0, 0x8, 0x3 },
[all …]
Dtda18271c2dd_maps.h3 HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
10 { 0, 0, 0x00, 0x00 }, /* HF_None */
11 { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */
12 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */
13 { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */
14 { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */
15 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */
16 { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */
17 { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */
18 { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */
[all …]
/linux-5.10/drivers/media/usb/gspca/
Dov534.c29 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
30 #define OV534_REG_SUBADDR 0xf2
31 #define OV534_REG_WRITE 0xf3
32 #define OV534_REG_READ 0xf4
33 #define OV534_REG_OPERATION 0xf5
34 #define OV534_REG_STATUS 0xf6
36 #define OV534_OP_WRITE_3 0x37
37 #define OV534_OP_WRITE_2 0x33
38 #define OV534_OP_READ_2 0xf9
96 .priv = 0},
[all …]
Dov534_9.c20 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
21 #define OV534_REG_SUBADDR 0xf2
22 #define OV534_REG_WRITE 0xf3
23 #define OV534_REG_READ 0xf4
24 #define OV534_REG_OPERATION 0xf5
25 #define OV534_REG_STATUS 0xf6
27 #define OV534_OP_WRITE_3 0x37
28 #define OV534_OP_WRITE_2 0x33
29 #define OV534_OP_READ_2 0xf9
54 #define QVGA_MODE 0
[all …]
Dconex.c53 .priv = 0},
69 usb_rcvctrlpipe(dev, 0), in reg_r()
70 0, in reg_r()
72 0, in reg_r()
76 index, gspca_dev->usb_buf[0]); in reg_r()
86 gspca_dev->usb_buf[0] = val; in reg_w_val()
88 usb_sndctrlpipe(dev, 0), in reg_w_val()
89 0, in reg_w_val()
91 0, in reg_w_val()
111 usb_sndctrlpipe(dev, 0), in reg_w()
[all …]
/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/linux-5.10/drivers/gpu/drm/i810/
Di810_drv.h60 #define DRIVER_PATCHLEVEL 0
139 #define I810_WRITE(reg, val) do { I810_DEREF(reg) = val; } while (0)
142 #define I810_WRITE16(reg, val) do { I810_DEREF16(reg) = val; } while (0)
144 #define I810_VERBOSE 0
157 } while (0)
164 } while (0)
172 } while (0)
174 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
175 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
177 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
[all …]
/linux-5.10/drivers/infiniband/hw/qib/
Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]
Dqib_7220_regs.h37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
Ddpcs_2_0_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h23 #define INSTR_MI_CLIENT 0x0
24 #define INSTR_BC_CLIENT 0x2
25 #define INSTR_RC_CLIENT 0x3
27 #define INSTR_SUBCLIENT_MASK 0x18000000
28 #define INSTR_MEDIA_SUBCLIENT 0x2
29 #define INSTR_26_TO_24_MASK 0x7000000
39 #define MI_NOOP MI_INSTR(0, 0)
40 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
41 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
46 #define MI_FLUSH MI_INSTR(0x04, 0)
[all …]
/linux-5.10/drivers/video/fbdev/sis/
Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]
/linux-5.10/drivers/media/tuners/
Dfc0013.c17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
24 return 0; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
38 return 0; in fc0013_readreg()
50 int i, ret = 0; in fc0013_init()
52 0x00, /* reg. 0x00: dummy */ in fc0013_init()
53 0x09, /* reg. 0x01 */ in fc0013_init()
54 0x16, /* reg. 0x02 */ in fc0013_init()
55 0x00, /* reg. 0x03 */ in fc0013_init()
56 0x00, /* reg. 0x04 */ in fc0013_init()
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_sh_mask.h7 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
8 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
9 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
10 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
11 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
12 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
13 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
14 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
16 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
17 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux-5.10/lib/crypto/
Dblake2s-selftest.c27 * for (i = 0; i < len; i++) {
28 * if (i && (i % 12) == 0)
30 * printf("0x%02x, ", vec[i]);
42 * key[0] = key[1] = 1;
46 * for (i = 0; i < BLAKE2S_TESTVEC_COUNT; ++i)
51 * for (i = 0; i < BLAKE2S_TESTVEC_COUNT; ++i) {
71 * return 0;
75 { 0xa1, },
76 { 0x7c, 0x89, },
77 { 0x74, 0x0e, 0xd4, },
[all …]
/linux-5.10/drivers/video/fbdev/
Dbw2.c54 #define BWTWO_REGISTER_OFFSET 0x400000
84 #define BWTWO_SR_RES_MASK 0x70
85 #define BWTWO_SR_1600_1280 0x50
86 #define BWTWO_SR_1152_900_76_A 0x40
87 #define BWTWO_SR_1152_900_76_B 0x60
88 #define BWTWO_SR_ID_MASK 0x0f
89 #define BWTWO_SR_ID_MONO 0x02
90 #define BWTWO_SR_ID_MONO_ECL 0x03
91 #define BWTWO_SR_ID_MSYNC 0x04
92 #define BWTWO_SR_ID_NOCONN 0x0a
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h25 …DC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
26 …DC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
27 …DC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
28 …DC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
29 …DC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
30 …DC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
31 …DC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
32 …DC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
33 …C_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
34 …C_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
[all …]

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