i915/gt/intel_gpu_commands.h

23 #define   INSTR_MI_CLIENT       0x0
24 #define   INSTR_BC_CLIENT       0x2
25 #define   INSTR_RC_CLIENT       0x3
27 #define INSTR_SUBCLIENT_MASK    0x18000000
28 #define   INSTR_MEDIA_SUBCLIENT 0x2
29 #define INSTR_26_TO_24_MASK	0x7000000
39 #define MI_NOOP			MI_INSTR(0, 0)
40 #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
41 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
46 #define MI_FLUSH		MI_INSTR(0x04, 0)
47 #define   MI_READ_FLUSH		(1 << 0)
53 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
54 #define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
55 #define   MI_ARB_ENABLE			(1<<0)
56 #define   MI_ARB_DISABLE		(0<<0)
57 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
58 #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
59 #define   MI_SUSPEND_FLUSH_EN	(1<<0)
60 #define MI_SET_APPID		MI_INSTR(0x0e, 0)
61 #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
62 #define   MI_OVERLAY_CONTINUE	(0x0<<21)
63 #define   MI_OVERLAY_ON		(0x1<<21)
64 #define   MI_OVERLAY_OFF	(0x2<<21)
65 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
66 #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
67 #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
70 #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
77 #define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
86 #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
91 #define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
94 #define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
97 #define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
100 #define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
105 #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
107 #define   MI_MM_SPACE_PHYSICAL		(0<<8)
111 #define   MI_RESTORE_INHIBIT		(1<<0)
114 #define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
116 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
117 #define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
119 #define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
127 #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
128 #define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
131 #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
139 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
144 #define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
145 #define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
147 #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
155 #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
156 #define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
157 #define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
158 #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
160 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
166 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
168 #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
175 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
177 #define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
179 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
180 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
181 #define   SC_UPDATE_SCISSOR       (0x1<<1)
182 #define   SC_ENABLE_MASK          (0x1<<0)
183 #define   SC_ENABLE               (0x1<<0)
184 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
185 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
186 #define   SCI_YMIN_MASK      (0xffff<<16)
187 #define   SCI_XMIN_MASK      (0xffff<<0)
188 #define   SCI_YMAX_MASK      (0xffff<<16)
189 #define   SCI_XMAX_MASK      (0xffff<<0)
190 #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
191 #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
192 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
193 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
194 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
195 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
196 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
197 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
198 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
200 #define COLOR_BLT_CMD			(2 << 29 | 0x40 << 22 | (5 - 2))
201 #define XY_COLOR_BLT_CMD		(2 << 29 | 0x50 << 22)
202 #define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
203 #define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
204 #define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
205 #define XY_MONO_SRC_COPY_IMM_BLT	(2 << 29 | 0x71 << 22 | 5)
209 #define   BLT_DEPTH_8			(0<<24)
213 #define   BLT_ROP_SRC_COPY		(0xcc<<16)
214 #define   BLT_ROP_COLOR_COPY		(0xf0<<16)
217 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
219 #define   DISPLAY_PLANE_A           (0<<20)
221 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
248 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
251 #define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
254 #define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0, 0x0)
255 #define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)
256 #define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1, op2)
257 #define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1)
258 #define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1)
259 #define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0, 0x0)
260 #define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0, 0x0)
261 #define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0, 0x0)
262 #define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0, 0x0)
263 #define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0, 0x0)
264 #define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)
265 #define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1, op2)
268 #define   MI_MATH_REG_SRCA		0x20
269 #define   MI_MATH_REG_SRCB		0x21
270 #define   MI_MATH_REG_ACCU		0x31
271 #define   MI_MATH_REG_ZF		0x32
272 #define   MI_MATH_REG_CF		0x33
277 #define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
278 #define MI_ARB_CHECK            MI_INSTR(0x05, 0)
279 #define MI_RS_CONTROL           MI_INSTR(0x06, 0)
280 #define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
281 #define MI_PREDICATE            MI_INSTR(0x0C, 0)
282 #define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
283 #define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
284 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
285 #define MI_URB_CLEAR            MI_INSTR(0x19, 0)
286 #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
287 #define MI_CLFLUSH              MI_INSTR(0x27, 0)
288 #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
289 #define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
290 #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
291 #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
292 #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
293 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
296 	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
297 #define BASE_ADDRESS_MODIFY		REG_BIT(0)
299 	((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
300 #define PIPELINE_SELECT_MEDIA	       REG_BIT(0)
302 	((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
304 	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
305 #define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
307 	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16))
309 	((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
310 #define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
311 #define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
313 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
315 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
317 	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
320 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
322 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
324 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
326 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
328 	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
330 #define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
332 #define COLOR_BLT     ((0x2<<29)|(0x40<<22))
333 #define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
351 	return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);  in gen8_noncanonical_addr()