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/linux-6.15/drivers/clk/mediatek/
Dclk-mt8186-vdec.c16 .set_ofs = 0x0,
17 .clr_ofs = 0x4,
18 .sta_ofs = 0x0,
22 .set_ofs = 0x190,
23 .clr_ofs = 0x190,
24 .sta_ofs = 0x190,
28 .set_ofs = 0x200,
29 .clr_ofs = 0x204,
30 .sta_ofs = 0x200,
34 .set_ofs = 0x8,
[all …]
/linux-6.15/drivers/media/platform/chips-media/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/linux-6.15/arch/arm64/boot/dts/freescale/
Dimx8mm-prt8mm.dts22 reg = <0x0 0x40000000 0 0x40000000>;
28 pinctrl-0 = <&pinctrl_gpio_leds>;
32 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
64 pinctrl-0 = <&pinctrl_i2c1>;
69 reg = <0x34>;
70 #sound-dai-cells = <0>;
77 pinctrl-0 = <&pinctrl_i2c2>;
82 reg = <0x60>;
83 regulator-name = "0V9_CORE";
94 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
Dimx8mm-evk.dts42 pinctrl-0 = <&pinctrl_flexspi>;
45 flash@0 {
46 reg = <0>;
60 pinctrl-0 = <&pinctrl_usdhc3>;
71 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
72 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
73 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
74 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
75 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
76 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
[all …]
Dimx8mm-var-som.dtsi18 reg = <0x0 0x40000000 0 0x80000000>;
24 pinctrl-0 = <&pinctrl_reg_eth_phy>;
71 pinctrl-0 = <&pinctrl_ecspi1>;
73 <&gpio1 0 GPIO_ACTIVE_LOW>;
79 touchscreen@0 {
80 reg = <0>;
83 pinctrl-0 = <&pinctrl_restouch>;
107 pinctrl-0 = <&pinctrl_fec1>;
116 #size-cells = <0>;
131 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mp-icore-mx8mp.dtsi31 pinctrl-0 = <&pinctrl_i2c1>;
39 pinctrl-0 = <&pinctrl_pmic>;
40 reg = <0x25>;
119 pinctrl-0 = <&pinctrl_usdhc3>;
128 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
129 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
135 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
141 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
142 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
143 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
[all …]
Dimx8mp-var-som.dtsi25 led-0 {
27 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
34 reg = <0x0 0x40000000 0 0xc0000000>,
35 <0x1 0x00000000 0 0xc0000000>;
55 states = <3300000 0x0 1800000 0x1>;
79 pinctrl-0 = <&pinctrl_i2c1>;
84 reg = <0x25>;
86 pinctrl-0 = <&pinctrl_pmic>;
178 pinctrl-0 = <&pinctrl_i2c3>;
184 reg = <0x20>;
[all …]
Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
62 pinctrl-0 = <&pinctrl_ecspi1>;
64 <&gpio1 0 GPIO_ACTIVE_LOW>;
70 touchscreen@0 {
71 reg = <0>;
74 pinctrl-0 = <&pinctrl_restouch>;
98 pinctrl-0 = <&pinctrl_fec1>;
108 #size-cells = <0>;
128 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-ucm-som.dtsi23 pwms = <&pwm2 0 3000000 0>;
24 brightness-levels = <0 255>;
33 pinctrl-0 = <&pinctrl_gpio_led>;
44 #clock-cells = <0>;
109 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
119 ethphy0: ethernet-phy@0 {
121 reg = <0>;
129 pinctrl-0 = <&pinctrl_i2c2>;
133 reg = <0x4b>;
[all …]
Dimx8mp-navqp.dts36 pinctrl-0 = <&pinctrl_gpio_led>;
38 led-0 {
49 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
78 pinctrl-0 = <&pinctrl_eqos>;
86 #size-cells = <0>;
88 ethphy0: ethernet-phy@0 {
90 reg = <0>;
106 pinctrl-0 = <&pinctrl_hdmi>;
125 pinctrl-0 = <&pinctrl_i2c1>;
130 reg = <0x25>;
[all …]
Dimx8mm-icore-mx8mm.dtsi30 pinctrl-0 = <&pinctrl_fec1>;
36 #size-cells = <0>;
50 pinctrl-0 = <&pinctrl_i2c1>;
55 reg = <0x08>;
148 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
149 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
150 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
151 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
152 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
153 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
[all …]
Dimx8mp-beacon-som.dtsi14 reg = <0x0 0x40000000 0 0xc0000000>,
15 <0x1 0x00000000 0 0xc0000000>;
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
49 pinctrl-0 = <&pinctrl_eqos>;
60 #size-cells = <0>;
77 snps,priority = <0x1>;
78 snps,map-to-dma-channel = <0>;
83 snps,priority = <0x2>;
89 snps,priority = <0x4>;
95 snps,priority = <0x8>;
[all …]
Dimx8mn-beacon-som.dtsi18 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
27 reg = <0x0 0x40000000 0 0x80000000>;
76 pinctrl-0 = <&pinctrl_fec1>;
86 #size-cells = <0>;
88 ethphy0: ethernet-phy@0 {
90 reg = <0>;
97 pinctrl-0 = <&pinctrl_flexspi>;
100 flash@0 {
101 reg = <0>;
114 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-beacon-som.dtsi17 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
26 reg = <0x0 0x40000000 0 0x80000000>;
68 pinctrl-0 = <&pinctrl_fec1>;
76 #size-cells = <0>;
78 ethphy0: ethernet-phy@0 {
80 reg = <0>;
87 pinctrl-0 = <&pinctrl_flexspi>;
90 flash@0 {
91 reg = <0>;
104 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-emtop-som.dtsi25 pinctrl-0 = <&pinctrl_gpio_led>;
27 led-0 {
54 pinctrl-0 = <&pinctrl_i2c1>;
59 reg = <0x25>;
61 pinctrl-0 = <&pinctrl_pmic>;
159 pinctrl-0 = <&pinctrl_uart2>;
165 pinctrl-0 = <&pinctrl_usdhc3>;
175 pinctrl-0 = <&pinctrl_wdog>;
183 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
184 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
[all …]
Dimx8mp-debix-model-a.dts38 pinctrl-0 = <&pinctrl_gpio_led>;
40 led-0 {
51 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
62 pinctrl-0 = <&pinctrl_reg_usb_hub>;
89 pinctrl-0 = <&pinctrl_eqos>;
97 #size-cells = <0>;
99 ethphy0: ethernet-phy@0 { /* RTL8211E */
101 reg = <0>;
115 pinctrl-0 = <&pinctrl_hdmi>;
134 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/linux-6.15/drivers/media/dvb-frontends/
Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/linux-6.15/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-v6_20.h10 #define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
11 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
12 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
13 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
14 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
15 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
16 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
17 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
Dphy-qcom-qmp-pcs-v6.h10 #define QPHY_V6_PCS_SW_RESET 0x000
11 #define QPHY_V6_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_PCS_START_CONTROL 0x044
14 #define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
Dphy-qcom-qmp-pcs-v6-n4.h10 #define QPHY_V6_N4_PCS_SW_RESET 0x000
11 #define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_N4_PCS_START_CONTROL 0x044
14 #define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
Dphy-qcom-qmp-pcs-v7.h10 #define QPHY_V7_PCS_SW_RESET 0x000
11 #define QPHY_V7_PCS_PCS_STATUS1 0x014
12 #define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V7_PCS_START_CONTROL 0x044
14 #define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
[all …]
/linux-6.15/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux-6.15/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux-6.15/Documentation/RCU/
Dlockdep-splat.rst30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]

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