| /qemu/tests/unit/ |
| H A D | test-crypto-afsplit.c | 44 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
64 "\x9e\xbc\xfe\x0c\x92\x79\xb3\xec"
76 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
85 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
96 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
98 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
100 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
102 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
110 return '0' + i; in hex()
121 for (i = 0; i < len; i++) { in hex_string()
[all …]
|
| H A D | test-crypto-der.c | 27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
32 "\xc8\x34\x0c\x12\x4f\x11\x90\xc6\xc2\xa5\xd0\xcd\xfb\xfc\x2c\x95"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
70 "\x8d\x11\x6d\x2d\xc6\x0c\x09\xe6\xf6\xb9\x8b\x87\x4c\x9f\x4d\x63"
73 "\xc3\x5f\xb2\x9e\x0c\x53\x04\x19\x34\x99\xe8\xe3\xe6\xd3\x2f\x45"
76 "\xab\x96\x7b\xf8\x9c\xf5\xb5\x9e\x2b\x13\x71\xe0\x01\x0c\x59\x1b"
82 "\x00\x8d\x21\x97\x0c\x29\x9a\xf8\x23\xf4\x76\x3b\xc1\x9b\x3e\xa8"
94 "\x10\x6a\x0c\x47\xe1\xf0\x36\x70\xd2\xa7\x57\x64\x47\x46\x9f\xca"
124 "\x0e\x03\x0c\x2e\xac\xf4\xdb\x60\x39\x40\x3e\x12\xc7\x40\xe7\xc9"
131 "\x4b\x69\xec\xf0\x5f\xf3\x88\x69\xcd\xbe\xed\x3c\xc5\x14\x5c\x0c"
[all …]
|
| H A D | test-crypto-ivgen.c | 40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
85 .sector = 0x1f2e3d4c5b6a7988ULL,
94 .sector = 0x1,
99 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
108 .sector = 0x1f2e3d4cULL,
113 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
[all …]
|
| H A D | test-crypto-pbkdf.c | 133 .out = "\x9c\xca\xd6\xd4\x68\x77\x0c\xd5"
163 .out = "\x0c\x60\xc8\x0f\x96\x1f\x0e\x71\xf3\xa9"
221 .key = "pass\0word",
223 .salt = "sa\0lt",
237 .nkey = 0,
288 .out = "\x13\x3b\x88\x0c\x0e\x52\xa2\x41"
322 .out = "\xd6\xcb\xd8\xa7\xdb\x0c\xa2\x2a"
344 #if 0
355 "\x53\x58\xf4\x0c\x39\xe7\x80\x89"
367 return '0' + i; in hex()
[all …]
|
| H A D | test-crypto-akcipher.c | 29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
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| H A D | test-crypto-xts.c | 46 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
48 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
49 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
50 0,
52 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
56 { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
[all …]
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| /qemu/tests/tcg/hexagon/ |
| H A D | hvx_histogram_input.h | 18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
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| /qemu/target/ppc/translate/ |
| H A D | vsx-ops.c.inc | 1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
|
| H A D | spe-ops.c.inc | 1 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
2 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
3 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
4 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
8 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
12 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
[all …]
|
| H A D | fp-ops.c.inc | 2 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
4 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
5 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
6 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
7 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
8 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
11 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
12 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
[all …]
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| /qemu/ebpf/ |
| H A D | rss.bpf.skeleton.h | 146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
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| /qemu/pc-bios/keymaps/ |
| H A D | sl | 3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
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| /qemu/ui/ |
| H A D | vgafont.h | 3 /* 0 0x00 '^@' */
4 0x00, /* 00000000 */
5 0x00, /* 00000000 */
6 0x00, /* 00000000 */
7 0x00, /* 00000000 */
8 0x00, /* 00000000 */
9 0x00, /* 00000000 */
10 0x00, /* 00000000 */
11 0x00, /* 00000000 */
12 0x00, /* 00000000 */
[all …]
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| /qemu/target/tricore/ |
| H A D | tricore-opcodes.h | 34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
290 OPCM_16_SR_SYSTEM = 0x00,
291 OPCM_16_SR_ACCU = 0x32,
293 OPC1_16_SRC_ADD = 0xc2,
294 OPC1_16_SRC_ADD_A15 = 0x92,
295 OPC1_16_SRC_ADD_15A = 0x9a,
296 OPC1_16_SRR_ADD = 0x42,
297 OPC1_16_SRR_ADD_A15 = 0x12,
298 OPC1_16_SRR_ADD_15A = 0x1a,
299 OPC1_16_SRC_ADD_A = 0xb0,
[all …]
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| /qemu/hw/misc/ |
| H A D | arm11scu.c | 24 case 0x00: /* Control. */ in mpcore_scu_read()
26 case 0x04: /* Configuration. */ in mpcore_scu_read()
29 case 0x08: /* CPU status. */ in mpcore_scu_read()
30 return 0; in mpcore_scu_read()
31 case 0x0c: /* Invalidate all. */ in mpcore_scu_read()
32 return 0; in mpcore_scu_read()
36 return 0; in mpcore_scu_read()
46 case 0: /* Control register. */ in mpcore_scu_write()
49 case 0x0c: /* Invalidate all. */ in mpcore_scu_write()
74 &mpcore_scu_ops, s, "mpcore-scu", 0x100); in arm11_scu_init()
|
| H A D | a9scu.c | 26 case 0x00: /* Control */ in a9_scu_read()
28 case 0x04: /* Configuration */ in a9_scu_read()
30 case 0x08: /* CPU Power Status */ in a9_scu_read()
32 case 0x0c: /* Invalidate All Registers In Secure State */ in a9_scu_read()
33 return 0; in a9_scu_read()
34 case 0x40: /* Filtering Start Address Register */ in a9_scu_read()
35 case 0x44: /* Filtering End Address Register */ in a9_scu_read()
37 return 0; in a9_scu_read()
38 case 0x50: /* SCU Access Control Register */ in a9_scu_read()
39 case 0x54: /* SCU Non-secure Access Control Register */ in a9_scu_read()
[all …]
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| /qemu/tests/bench/ |
| H A D | test_akcipher_keys.c.inc | 12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
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| /qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 38 #define PCI_VENDOR_ID 0x00 /* 16 bits */
39 #define PCI_DEVICE_ID 0x02 /* 16 bits */
40 #define PCI_COMMAND 0x04 /* 16 bits */
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
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| /qemu/target/ppc/ |
| H A D | translate.c | 46 #define CPU_SINGLE_STEP 0x1
47 #define CPU_BRANCH_STEP 0x2
55 # define LOG_DISAS(...) do { } while (0)
93 for (i = 0; i < 8; i++) { in ppc_translate_init()
101 for (i = 0; i < 32; i++) { in ppc_translate_init()
226 # define NARROW_MODE(C) 0
230 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
363 target_ulong dbsr = 0; in gen_debug_exception()
410 #if 0 in spr_noaccess()
411 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); in spr_noaccess()
[all …]
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| /qemu/hw/arm/ |
| H A D | aspeed_eeprom.c | 12 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
13 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
14 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
15 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
16 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
17 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
18 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
19 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
20 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
21 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x54, 0x69, 0x6f, 0x67, 0x61,
[all …]
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| /qemu/hw/block/ |
| H A D | m25p80_sfdp.c | 25 0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
26 0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
27 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
28 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
29 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
30 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
31 0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
32 0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
33 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
34 0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
[all …]
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| /qemu/include/hw/misc/ |
| H A D | mos6522.h | 37 #define SR_CTRL 0x1c /* Shift register control bits */
38 #define SR_EXT 0x0c /* Shift on external clock */
39 #define SR_OUT 0x10 /* Shift out if 1 */
42 #define IER_SET 0x80 /* set bits in IER */
43 #define IER_CLR 0 /* clear bits in IER */
45 #define CA2_INT_BIT 0
64 #define T1MODE 0xc0 /* Timer 1 mode */
65 #define T1MODE_CONT 0x40 /* continuous interrupts */
68 #define CB2_CTRL_MASK 0xe0
70 #define CB1_CTRL_MASK 0x10
[all …]
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| /qemu/hw/display/ |
| H A D | vga_regs.h | 32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
38 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
39 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
40 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
41 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
[all …]
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| /qemu/tests/tcg/s390x/ |
| H A D | mvo.c | 6 uint8_t dest[6] = {0xff, 0x77, 0x88, 0x99, 0x0c, 0xff}; in main()
7 uint8_t src[5] = {0xee, 0x12, 0x34, 0x56, 0xee}; in main()
8 uint8_t expected[6] = {0xff, 0x01, 0x23, 0x45, 0x6c, 0xff}; in main()
12 " mvo 0(4,%[dest]),0(3,%[src])\n" in main()
18 for (i = 0; i < sizeof(expected); i++) { in main()
24 return 0; in main()
|
| /qemu/hw/m68k/ |
| H A D | mcf_intc.c | 44 best_level = 0; in mcf_intc_update()
47 for (i = 0; i < 64; i++) { in mcf_intc_update()
48 if ((active & 1) != 0 && s->icr[i] >= best_level) { in mcf_intc_update()
64 offset = addr & 0xff; in mcf_intc_read()
65 if (offset >= 0x40 && offset < 0x80) { in mcf_intc_read()
66 return s->icr[offset - 0x40]; in mcf_intc_read()
69 case 0x00: in mcf_intc_read()
71 case 0x04: in mcf_intc_read()
73 case 0x08: in mcf_intc_read()
75 case 0x0c: in mcf_intc_read()
[all …]
|