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/qemu/target/ppc/translate/
H A Dspe-ops.c.inc1 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
2 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
3 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
4 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
8 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
12 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
[all …]
H A Dspe-impl.c.inc130 tcg_gen_addi_i32(ret, arg1, 0x8000);
166 tcg_gen_andi_i32(t0, arg2, 0x3F);
171 tcg_gen_movi_i32(ret, 0);
182 tcg_gen_andi_i32(t0, arg2, 0x3F);
187 tcg_gen_movi_i32(ret, 0);
198 tcg_gen_andi_i32(t0, arg2, 0x3F);
203 tcg_gen_movi_i32(ret, 0);
210 tcg_gen_andi_i32(t0, arg2, 0x1F);
272 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
368 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
[all …]
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
/qemu/tests/unit/
H A Dtest-crypto-afsplit.c44 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
76 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
85 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
96 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
98 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
100 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
102 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
110 return '0' + i; in hex()
121 for (i = 0; i < len; i++) { in hex_string()
122 hexstr[i * 2] = hex((bytes[i] >> 4) & 0xf); in hex_string()
[all …]
H A Dtest-crypto-ivgen.c40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
85 .sector = 0x1f2e3d4c5b6a7988ULL,
94 .sector = 0x1,
99 "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
102 "\x1c\x7a\x2d\06\x2d\x0b\x65\x46",
108 .sector = 0x1f2e3d4cULL,
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
86 "\xdc\x00\xd1\xd6\x1b\xa6\xba\x45\xe2\x77\x53\x31\xbf\xe1\xec\x0b"
106 "\xae\x3f\x49\x54\xd2\x2b\xac\x28\x39\x88\x31\x42\x12\x08\xea\x0b"
114 "\x9e\x48\x36\x62\x0b\x05\xfa\x38\xc1\x06\x04\x58\x95\x4d\x25\x13"
115 "\x6d\x0b\x12\x0b\xc9\x6d\x59\xfc\x33\x03\x36\x01\x12\x09\x72\x74"
144 "\x24\xa1\xad\x13\x35\x31\xc0\x0b\xf1\xd2\x06\x7c\x94\x1a\x21\x2f"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
169 "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */
[all …]
H A Dtest-crypto-xts.c46 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
48 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
49 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
50 0,
52 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
56 { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
[all …]
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_input.h18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_shll_s_w.c9 rt = 0x82345678; in main()
10 result = 0x82345678; in main()
11 resultdsp = 0x00; in main()
14 ("shll_s.w %0, %2, 0x0\n\t" in main()
19 dsp = (dsp >> 22) & 0x01; in main()
23 rt = 0x82345678; in main()
24 result = 0x80000000; in main()
25 resultdsp = 0x01; in main()
28 ("shll_s.w %0, %2, 0x0B\n\t" in main()
33 dsp = (dsp >> 22) & 0x01; in main()
[all …]
H A Dtest_dsp_r1_shll_s_ph.c9 rt = 0x12345678; in main()
10 result = 0x7FFF7FFF; in main()
11 resultdsp = 0x01; in main()
14 ("shll_s.ph %0, %2, 0x0B\n\t" in main()
19 dsp = (dsp >> 22) & 0x01; in main()
23 return 0; in main()
H A Dtest_dsp_r2_cmpgdu_le_qb.c10 rs = 0x11777066; in main()
11 rt = 0x55AA70FF; in main()
12 result = 0x0F; in main()
14 ("cmpgdu.le.qb %0, %2, %3\n\t" in main()
19 dsp = (dsp >> 24) & 0x0F; in main()
23 rs = 0x11777066; in main()
24 rt = 0x11707066; in main()
25 result = 0x0B; in main()
27 ("cmpgdu.le.qb %0, %2, %3\n\t" in main()
32 dsp = (dsp >> 24) & 0x0F; in main()
[all …]
H A Dtest_dsp_r1_shllv_s_w.c9 rs = 0x0B; in main()
10 rt = 0x12345678; in main()
11 result = 0x7FFFFFFF; in main()
12 resultdsp = 0x01; in main()
15 ("shllv_s.w %0, %2, %3\n\t" in main()
20 dsp = (dsp >> 22) & 0x01; in main()
24 rs = 0x0; in main()
25 rt = 0x12345678; in main()
26 result = 0x12345678; in main()
27 resultdsp = 0x01; in main()
[all …]
H A Dtest_dsp_r1_shllv_s_ph.c9 rs = 0x0; in main()
10 rt = 0x12345678; in main()
11 result = 0x12345678; in main()
12 resultdsp = 0x0; in main()
15 ("shllv_s.ph %0, %2, %3\n\t" in main()
20 dsp = (dsp >> 22) & 0x01; in main()
24 rs = 0x0B; in main()
25 rt = 0x12345678; in main()
26 result = 0x7FFF7FFF; in main()
27 resultdsp = 0x01; in main()
[all …]
H A Dtest_dsp_r1_shllv_ph.c9 rs = 0x0; in main()
10 rt = 0x12345678; in main()
11 result = 0x12345678; in main()
12 resultdsp = 0; in main()
15 ("shllv.ph %0, %2, %3\n\t" in main()
20 dsp = (dsp >> 22) & 0x01; in main()
24 rs = 0x0B; in main()
25 rt = 0x12345678; in main()
26 result = 0xA000C000; in main()
30 ("shllv.ph %0, %2, %3\n\t" in main()
[all …]
H A Dtest_dsp_r1_shll_ph.c9 rt = 0x12345678; in main()
10 result = 0xA000C000; in main()
14 ("wrdsp $0\n\t" in main()
15 "shll.ph %0, %2, 0x0B\n\t" in main()
20 dsp = (dsp >> 22) & 0x01; in main()
24 rt = 0x7fff8000; in main()
25 result = 0xfffe0000; in main()
29 ("wrdsp $0\n\t" in main()
30 "shll.ph %0, %2, 0x01\n\t" in main()
35 dsp = (dsp >> 22) & 0x01; in main()
[all …]
/qemu/pc-bios/keymaps/
H A Dsl3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
/qemu/tests/bench/
H A Dtest_akcipher_keys.c.inc12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/hw/display/
H A Dcirrus_vga.c66 // sequencer 0x07
67 #define CIRRUS_SR7_BPP_VGA 0x00
68 #define CIRRUS_SR7_BPP_SVGA 0x01
69 #define CIRRUS_SR7_BPP_MASK 0x0e
70 #define CIRRUS_SR7_BPP_8 0x00
71 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
72 #define CIRRUS_SR7_BPP_24 0x04
73 #define CIRRUS_SR7_BPP_16 0x06
74 #define CIRRUS_SR7_BPP_32 0x08
75 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
[all …]
H A Dvga_regs.h32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
38 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
39 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
40 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
41 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
[all …]
/qemu/linux-user/include/host/s390x/
H A Dhost-signal.h49 switch (pinsn[0] >> 8) { in host_signal_write()
50 case 0x50: /* ST */ in host_signal_write()
51 case 0x42: /* STC */ in host_signal_write()
52 case 0x40: /* STH */ in host_signal_write()
53 case 0x44: /* EX */ in host_signal_write()
54 case 0xba: /* CS */ in host_signal_write()
55 case 0xbb: /* CDS */ in host_signal_write()
57 case 0xc4: /* RIL format insns */ in host_signal_write()
58 switch (pinsn[0] & 0xf) { in host_signal_write()
59 case 0xf: /* STRL */ in host_signal_write()
[all …]
/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
[all …]
/qemu/include/hw/display/
H A Dbochs-vbe.h12 #define VBE_DISPI_INDEX_ID 0x0
13 #define VBE_DISPI_INDEX_XRES 0x1
14 #define VBE_DISPI_INDEX_YRES 0x2
15 #define VBE_DISPI_INDEX_BPP 0x3
16 #define VBE_DISPI_INDEX_ENABLE 0x4
17 #define VBE_DISPI_INDEX_BANK 0x5
18 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
19 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
20 #define VBE_DISPI_INDEX_X_OFFSET 0x8
21 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
[all …]
/qemu/tests/qtest/migration/aarch64/
H A Da-b-kernel.h7 0x00, 0x10, 0x38, 0xd5, 0x00, 0xf8, 0x7f, 0x92, 0x00, 0x10, 0x18, 0xd5,
8 0xdf, 0x3f, 0x03, 0xd5, 0x00, 0x02, 0xa8, 0xd2, 0x01, 0xc8, 0xa8, 0xd2,
9 0x23, 0x08, 0x80, 0x52, 0x02, 0x20, 0xa1, 0xd2, 0x43, 0x00, 0x00, 0x39,
10 0x03, 0x00, 0x80, 0x52, 0xe4, 0x03, 0x00, 0xaa, 0x83, 0x00, 0x00, 0x39,
11 0x84, 0x04, 0x40, 0x91, 0x9f, 0x00, 0x01, 0xeb, 0xad, 0xff, 0xff, 0x54,
12 0x05, 0x00, 0x80, 0x52, 0xe4, 0x03, 0x00, 0xaa, 0x83, 0x00, 0x40, 0x39,
13 0x63, 0x04, 0x00, 0x11, 0x83, 0x00, 0x00, 0x39, 0x24, 0x7e, 0x0b, 0xd5,
14 0x84, 0x04, 0x40, 0x91, 0x9f, 0x00, 0x01, 0xeb, 0x4b, 0xff, 0xff, 0x54,
15 0xa5, 0x04, 0x00, 0x11, 0xa5, 0x10, 0x00, 0x12, 0xbf, 0x00, 0x00, 0x71,
16 0xa1, 0xfe, 0xff, 0x54, 0x43, 0x08, 0x80, 0x52, 0x43, 0x00, 0x00, 0x39,
[all …]

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