Lines Matching +full:0 +full:x0b
66 // sequencer 0x07
67 #define CIRRUS_SR7_BPP_VGA 0x00
68 #define CIRRUS_SR7_BPP_SVGA 0x01
69 #define CIRRUS_SR7_BPP_MASK 0x0e
70 #define CIRRUS_SR7_BPP_8 0x00
71 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
72 #define CIRRUS_SR7_BPP_24 0x04
73 #define CIRRUS_SR7_BPP_16 0x06
74 #define CIRRUS_SR7_BPP_32 0x08
75 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77 // sequencer 0x0f
78 #define CIRRUS_MEMSIZE_512k 0x08
79 #define CIRRUS_MEMSIZE_1M 0x10
80 #define CIRRUS_MEMSIZE_2M 0x18
81 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83 // sequencer 0x12
84 #define CIRRUS_CURSOR_SHOW 0x01
85 #define CIRRUS_CURSOR_HIDDENPEL 0x02
86 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88 // sequencer 0x17
89 #define CIRRUS_BUSTYPE_VLBFAST 0x10
90 #define CIRRUS_BUSTYPE_PCI 0x20
91 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
92 #define CIRRUS_BUSTYPE_ISA 0x38
93 #define CIRRUS_MMIO_ENABLE 0x04
94 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
95 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97 // control 0x0b
98 #define CIRRUS_BANKING_DUAL 0x01
99 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101 // control 0x30
102 #define CIRRUS_BLTMODE_BACKWARDS 0x01
103 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
104 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
105 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
106 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
107 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
108 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
109 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
110 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
111 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
112 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114 // control 0x31
115 #define CIRRUS_BLT_BUSY 0x01
116 #define CIRRUS_BLT_START 0x02
117 #define CIRRUS_BLT_RESET 0x04
118 #define CIRRUS_BLT_FIFOUSED 0x10
119 #define CIRRUS_BLT_AUTOSTART 0x80
121 // control 0x32
122 #define CIRRUS_ROP_0 0x00
123 #define CIRRUS_ROP_SRC_AND_DST 0x05
124 #define CIRRUS_ROP_NOP 0x06
125 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
126 #define CIRRUS_ROP_NOTDST 0x0b
127 #define CIRRUS_ROP_SRC 0x0d
128 #define CIRRUS_ROP_1 0x0e
129 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
130 #define CIRRUS_ROP_SRC_XOR_DST 0x59
131 #define CIRRUS_ROP_SRC_OR_DST 0x6d
132 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
133 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
134 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
135 #define CIRRUS_ROP_NOTSRC 0xd0
136 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
137 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
142 // control 0x33
143 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
144 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
145 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
148 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
149 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
150 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
151 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
152 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
153 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
154 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
155 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
156 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
157 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
158 #define CIRRUS_MMIO_BLTROP 0x1a // byte
159 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
161 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
162 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
163 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
165 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
169 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
170 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
171 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
172 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
173 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
174 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
175 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
176 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
178 #define CIRRUS_PNPMMIO_SIZE 0x1000
216 if (pitch < 0) { in blit_region_is_unsafe()
237 assert(s->cirrus_blt_width > 0); in blit_is_unsafe()
238 assert(s->cirrus_blt_height > 0); in blit_is_unsafe()
311 #define ROP_NAME 0
312 #define ROP_FN(d, s) 0
332 #define ROP_FN(d, s) ~0
592 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); in cirrus_bitblt_fgcol()
597 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); in cirrus_bitblt_fgcol()
601 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | in cirrus_bitblt_fgcol()
602 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); in cirrus_bitblt_fgcol()
616 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); in cirrus_bitblt_bgcol()
621 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); in cirrus_bitblt_bgcol()
625 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | in cirrus_bitblt_bgcol()
626 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); in cirrus_bitblt_bgcol()
640 if (off_pitch < 0) { in cirrus_invalidate_region()
644 for (y = 0; y < lines; y++) { in cirrus_invalidate_region()
653 memory_region_set_dirty(&s->vga.vram, 0, off_cur_end); in cirrus_invalidate_region()
681 return 0; in cirrus_bitblt_common_patterncopy()
686 return 0; in cirrus_bitblt_common_patterncopy()
690 videosrc ? s->cirrus_blt_srcaddr : 0, in cirrus_bitblt_common_patterncopy()
691 s->cirrus_blt_dstpitch, 0, in cirrus_bitblt_common_patterncopy()
706 return 0; in cirrus_bitblt_solidfill()
732 int sx = 0, sy = 0; in cirrus_do_copy()
733 int dx = 0, dy = 0; in cirrus_do_copy()
734 int depth = 0; in cirrus_do_copy()
735 int notify = 0; in cirrus_do_copy()
745 return 0; in cirrus_do_copy()
761 if (s->cirrus_blt_dstpitch < 0) { in cirrus_do_copy()
769 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && in cirrus_do_copy()
800 return 0; in cirrus_bitblt_videotovideo_copy()
818 if (s->cirrus_srccounter > 0) { in cirrus_bitblt_cputovideo_next()
822 s->cirrus_srccounter = 0; in cirrus_bitblt_cputovideo_next()
828 0, 0, 0, s->cirrus_blt_width, 1); in cirrus_bitblt_cputovideo_next()
829 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, in cirrus_bitblt_cputovideo_next()
833 if (s->cirrus_srccounter <= 0) in cirrus_bitblt_cputovideo_next()
858 s->vga.gr[0x31] &= in cirrus_bitblt_reset()
860 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] in cirrus_bitblt_reset()
861 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
862 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
863 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
864 s->cirrus_srccounter = 0; in cirrus_bitblt_reset()
875 return 0; in cirrus_bitblt_cputovideo()
879 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; in cirrus_bitblt_cputovideo()
880 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; in cirrus_bitblt_cputovideo()
918 return 0; in cirrus_bitblt_videotocpu()
943 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY; in cirrus_bitblt_start()
945 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; in cirrus_bitblt_start()
946 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; in cirrus_bitblt_start()
947 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); in cirrus_bitblt_start()
948 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); in cirrus_bitblt_start()
950 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); in cirrus_bitblt_start()
952 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); in cirrus_bitblt_start()
953 s->cirrus_blt_mode = s->vga.gr[0x30]; in cirrus_bitblt_start()
954 s->cirrus_blt_modeext = s->vga.gr[0x33]; in cirrus_bitblt_start()
955 blt_rop = s->vga.gr[0x32]; in cirrus_bitblt_start()
969 s->vga.gr[0x2f]); in cirrus_bitblt_start()
1086 old_value = s->vga.gr[0x31]; in cirrus_write_bitblt()
1087 s->vga.gr[0x31] = reg_value; in cirrus_write_bitblt()
1089 if (((old_value & CIRRUS_BLT_RESET) != 0) && in cirrus_write_bitblt()
1090 ((reg_value & CIRRUS_BLT_RESET) == 0)) { in cirrus_write_bitblt()
1092 } else if (((old_value & CIRRUS_BLT_START) == 0) && in cirrus_write_bitblt()
1093 ((reg_value & CIRRUS_BLT_START) != 0)) { in cirrus_write_bitblt()
1111 line_offset = s->vga.cr[0x13] in cirrus_get_params()
1112 | ((s->vga.cr[0x1b] & 0x10) << 4); in cirrus_get_params()
1116 params->start_addr = (s->vga.cr[0x0c] << 8) in cirrus_get_params()
1117 | s->vga.cr[0x0d] in cirrus_get_params()
1118 | ((s->vga.cr[0x1b] & 0x01) << 16) in cirrus_get_params()
1119 | ((s->vga.cr[0x1b] & 0x0c) << 15) in cirrus_get_params()
1120 | ((s->vga.cr[0x1d] & 0x80) << 12); in cirrus_get_params()
1122 params->line_compare = s->vga.cr[0x18] | in cirrus_get_params()
1123 ((s->vga.cr[0x07] & 0x10) << 4) | in cirrus_get_params()
1124 ((s->vga.cr[0x09] & 0x40) << 3); in cirrus_get_params()
1127 params->hpel_split = s->vga.ar[VGA_ATC_MODE] & 0x20; in cirrus_get_params()
1134 switch (s->cirrus_hidden_dac_data & 0xf) { in cirrus_get_bpp16_depth()
1135 case 0: in cirrus_get_bpp16_depth()
1143 "cirrus: invalid DAC value 0x%x in 16bpp\n", in cirrus_get_bpp16_depth()
1144 (s->cirrus_hidden_dac_data & 0xf)); in cirrus_get_bpp16_depth()
1156 if ((s->vga.sr[0x07] & 0x01) != 0) { in cirrus_get_bpp()
1158 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { in cirrus_get_bpp()
1176 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); in cirrus_get_bpp()
1183 ret = 0; in cirrus_get_bpp()
1193 width = (s->cr[0x01] + 1) * 8; in cirrus_get_resolution()
1194 height = s->cr[0x12] | in cirrus_get_resolution()
1195 ((s->cr[0x07] & 0x02) << 7) | in cirrus_get_resolution()
1196 ((s->cr[0x07] & 0x40) << 3); in cirrus_get_resolution()
1199 if (s->cr[0x1a] & 0x01) in cirrus_get_resolution()
1216 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ in cirrus_update_bank_ptr()
1217 offset = s->vga.gr[0x09 + bank_index]; in cirrus_update_bank_ptr()
1219 offset = s->vga.gr[0x09]; in cirrus_update_bank_ptr()
1221 if ((s->vga.gr[0x0b] & 0x20) != 0) in cirrus_update_bank_ptr()
1227 limit = 0; in cirrus_update_bank_ptr()
1231 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { in cirrus_update_bank_ptr()
1232 if (limit > 0x8000) { in cirrus_update_bank_ptr()
1233 offset += 0x8000; in cirrus_update_bank_ptr()
1234 limit -= 0x8000; in cirrus_update_bank_ptr()
1236 limit = 0; in cirrus_update_bank_ptr()
1240 if (limit > 0) { in cirrus_update_bank_ptr()
1244 s->cirrus_bank_base[bank_index] = 0; in cirrus_update_bank_ptr()
1245 s->cirrus_bank_limit[bank_index] = 0; in cirrus_update_bank_ptr()
1251 * I/O access between 0x3c4-0x3c5
1258 case 0x00: // Standard VGA in cirrus_vga_read_sr()
1259 case 0x01: // Standard VGA in cirrus_vga_read_sr()
1260 case 0x02: // Standard VGA in cirrus_vga_read_sr()
1261 case 0x03: // Standard VGA in cirrus_vga_read_sr()
1262 case 0x04: // Standard VGA in cirrus_vga_read_sr()
1264 case 0x06: // Unlock Cirrus extensions in cirrus_vga_read_sr()
1266 case 0x10: in cirrus_vga_read_sr()
1267 case 0x30: in cirrus_vga_read_sr()
1268 case 0x50: in cirrus_vga_read_sr()
1269 case 0x70: // Graphics Cursor X in cirrus_vga_read_sr()
1270 case 0x90: in cirrus_vga_read_sr()
1271 case 0xb0: in cirrus_vga_read_sr()
1272 case 0xd0: in cirrus_vga_read_sr()
1273 case 0xf0: // Graphics Cursor X in cirrus_vga_read_sr()
1274 return s->vga.sr[0x10]; in cirrus_vga_read_sr()
1275 case 0x11: in cirrus_vga_read_sr()
1276 case 0x31: in cirrus_vga_read_sr()
1277 case 0x51: in cirrus_vga_read_sr()
1278 case 0x71: // Graphics Cursor Y in cirrus_vga_read_sr()
1279 case 0x91: in cirrus_vga_read_sr()
1280 case 0xb1: in cirrus_vga_read_sr()
1281 case 0xd1: in cirrus_vga_read_sr()
1282 case 0xf1: // Graphics Cursor Y in cirrus_vga_read_sr()
1283 return s->vga.sr[0x11]; in cirrus_vga_read_sr()
1284 case 0x05: // ??? in cirrus_vga_read_sr()
1285 case 0x07: // Extended Sequencer Mode in cirrus_vga_read_sr()
1286 case 0x08: // EEPROM Control in cirrus_vga_read_sr()
1287 case 0x09: // Scratch Register 0 in cirrus_vga_read_sr()
1288 case 0x0a: // Scratch Register 1 in cirrus_vga_read_sr()
1289 case 0x0b: // VCLK 0 in cirrus_vga_read_sr()
1290 case 0x0c: // VCLK 1 in cirrus_vga_read_sr()
1291 case 0x0d: // VCLK 2 in cirrus_vga_read_sr()
1292 case 0x0e: // VCLK 3 in cirrus_vga_read_sr()
1293 case 0x0f: // DRAM Control in cirrus_vga_read_sr()
1294 case 0x12: // Graphics Cursor Attribute in cirrus_vga_read_sr()
1295 case 0x13: // Graphics Cursor Pattern Address in cirrus_vga_read_sr()
1296 case 0x14: // Scratch Register 2 in cirrus_vga_read_sr()
1297 case 0x15: // Scratch Register 3 in cirrus_vga_read_sr()
1298 case 0x16: // Performance Tuning Register in cirrus_vga_read_sr()
1299 case 0x17: // Configuration Readback and Extended Control in cirrus_vga_read_sr()
1300 case 0x18: // Signature Generator Control in cirrus_vga_read_sr()
1301 case 0x19: // Signal Generator Result in cirrus_vga_read_sr()
1302 case 0x1a: // Signal Generator Result in cirrus_vga_read_sr()
1303 case 0x1b: // VCLK 0 Denominator & Post in cirrus_vga_read_sr()
1304 case 0x1c: // VCLK 1 Denominator & Post in cirrus_vga_read_sr()
1305 case 0x1d: // VCLK 2 Denominator & Post in cirrus_vga_read_sr()
1306 case 0x1e: // VCLK 3 Denominator & Post in cirrus_vga_read_sr()
1307 case 0x1f: // BIOS Write Enable and MCLK select in cirrus_vga_read_sr()
1314 "cirrus: inport sr_index 0x%02x\n", s->vga.sr_index); in cirrus_vga_read_sr()
1315 return 0xff; in cirrus_vga_read_sr()
1322 case 0x00: // Standard VGA in cirrus_vga_write_sr()
1323 case 0x01: // Standard VGA in cirrus_vga_write_sr()
1324 case 0x02: // Standard VGA in cirrus_vga_write_sr()
1325 case 0x03: // Standard VGA in cirrus_vga_write_sr()
1326 case 0x04: // Standard VGA in cirrus_vga_write_sr()
1331 case 0x06: // Unlock Cirrus extensions in cirrus_vga_write_sr()
1332 val &= 0x17; in cirrus_vga_write_sr()
1333 if (val == 0x12) { in cirrus_vga_write_sr()
1334 s->vga.sr[s->vga.sr_index] = 0x12; in cirrus_vga_write_sr()
1336 s->vga.sr[s->vga.sr_index] = 0x0f; in cirrus_vga_write_sr()
1339 case 0x10: in cirrus_vga_write_sr()
1340 case 0x30: in cirrus_vga_write_sr()
1341 case 0x50: in cirrus_vga_write_sr()
1342 case 0x70: // Graphics Cursor X in cirrus_vga_write_sr()
1343 case 0x90: in cirrus_vga_write_sr()
1344 case 0xb0: in cirrus_vga_write_sr()
1345 case 0xd0: in cirrus_vga_write_sr()
1346 case 0xf0: // Graphics Cursor X in cirrus_vga_write_sr()
1347 s->vga.sr[0x10] = val; in cirrus_vga_write_sr()
1350 case 0x11: in cirrus_vga_write_sr()
1351 case 0x31: in cirrus_vga_write_sr()
1352 case 0x51: in cirrus_vga_write_sr()
1353 case 0x71: // Graphics Cursor Y in cirrus_vga_write_sr()
1354 case 0x91: in cirrus_vga_write_sr()
1355 case 0xb1: in cirrus_vga_write_sr()
1356 case 0xd1: in cirrus_vga_write_sr()
1357 case 0xf1: // Graphics Cursor Y in cirrus_vga_write_sr()
1358 s->vga.sr[0x11] = val; in cirrus_vga_write_sr()
1361 case 0x07: // Extended Sequencer Mode in cirrus_vga_write_sr()
1364 case 0x08: // EEPROM Control in cirrus_vga_write_sr()
1365 case 0x09: // Scratch Register 0 in cirrus_vga_write_sr()
1366 case 0x0a: // Scratch Register 1 in cirrus_vga_write_sr()
1367 case 0x0b: // VCLK 0 in cirrus_vga_write_sr()
1368 case 0x0c: // VCLK 1 in cirrus_vga_write_sr()
1369 case 0x0d: // VCLK 2 in cirrus_vga_write_sr()
1370 case 0x0e: // VCLK 3 in cirrus_vga_write_sr()
1371 case 0x0f: // DRAM Control in cirrus_vga_write_sr()
1372 case 0x13: // Graphics Cursor Pattern Address in cirrus_vga_write_sr()
1373 case 0x14: // Scratch Register 2 in cirrus_vga_write_sr()
1374 case 0x15: // Scratch Register 3 in cirrus_vga_write_sr()
1375 case 0x16: // Performance Tuning Register in cirrus_vga_write_sr()
1376 case 0x18: // Signature Generator Control in cirrus_vga_write_sr()
1377 case 0x19: // Signature Generator Result in cirrus_vga_write_sr()
1378 case 0x1a: // Signature Generator Result in cirrus_vga_write_sr()
1379 case 0x1b: // VCLK 0 Denominator & Post in cirrus_vga_write_sr()
1380 case 0x1c: // VCLK 1 Denominator & Post in cirrus_vga_write_sr()
1381 case 0x1d: // VCLK 2 Denominator & Post in cirrus_vga_write_sr()
1382 case 0x1e: // VCLK 3 Denominator & Post in cirrus_vga_write_sr()
1383 case 0x1f: // BIOS Write Enable and MCLK select in cirrus_vga_write_sr()
1390 case 0x12: // Graphics Cursor Attribute in cirrus_vga_write_sr()
1391 s->vga.sr[0x12] = val; in cirrus_vga_write_sr()
1398 case 0x17: // Configuration Readback and Extended Control in cirrus_vga_write_sr()
1399 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) in cirrus_vga_write_sr()
1400 | (val & 0xc7); in cirrus_vga_write_sr()
1405 "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n", in cirrus_vga_write_sr()
1413 * I/O access at 0x3c6
1420 s->cirrus_hidden_dac_lockindex = 0; in cirrus_read_hidden_dac()
1423 return 0xff; in cirrus_read_hidden_dac()
1434 s->cirrus_hidden_dac_lockindex = 0; in cirrus_write_hidden_dac()
1439 * I/O access at 0x3c9
1447 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { in cirrus_vga_read_palette()
1448 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + in cirrus_vga_read_palette()
1454 s->vga.dac_sub_index = 0; in cirrus_vga_read_palette()
1464 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { in cirrus_vga_write_palette()
1465 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], in cirrus_vga_write_palette()
1471 s->vga.dac_sub_index = 0; in cirrus_vga_write_palette()
1478 * I/O access between 0x3ce-0x3cf
1485 case 0x00: // Standard VGA, BGCOLOR 0x000000ff in cirrus_vga_read_gr()
1487 case 0x01: // Standard VGA, FGCOLOR 0x000000ff in cirrus_vga_read_gr()
1489 case 0x02: // Standard VGA in cirrus_vga_read_gr()
1490 case 0x03: // Standard VGA in cirrus_vga_read_gr()
1491 case 0x04: // Standard VGA in cirrus_vga_read_gr()
1492 case 0x06: // Standard VGA in cirrus_vga_read_gr()
1493 case 0x07: // Standard VGA in cirrus_vga_read_gr()
1494 case 0x08: // Standard VGA in cirrus_vga_read_gr()
1496 case 0x05: // Standard VGA, Cirrus extended mode in cirrus_vga_read_gr()
1501 if (reg_index < 0x3a) { in cirrus_vga_read_gr()
1505 "cirrus: inport gr_index 0x%02x\n", reg_index); in cirrus_vga_read_gr()
1506 return 0xff; in cirrus_vga_read_gr()
1515 case 0x00: // Standard VGA, BGCOLOR 0x000000ff in cirrus_vga_write_gr()
1519 case 0x01: // Standard VGA, FGCOLOR 0x000000ff in cirrus_vga_write_gr()
1523 case 0x02: // Standard VGA in cirrus_vga_write_gr()
1524 case 0x03: // Standard VGA in cirrus_vga_write_gr()
1525 case 0x04: // Standard VGA in cirrus_vga_write_gr()
1526 case 0x06: // Standard VGA in cirrus_vga_write_gr()
1527 case 0x07: // Standard VGA in cirrus_vga_write_gr()
1528 case 0x08: // Standard VGA in cirrus_vga_write_gr()
1531 case 0x05: // Standard VGA, Cirrus extended mode in cirrus_vga_write_gr()
1532 s->vga.gr[reg_index] = reg_value & 0x7f; in cirrus_vga_write_gr()
1535 case 0x09: // bank offset #0 in cirrus_vga_write_gr()
1536 case 0x0A: // bank offset #1 in cirrus_vga_write_gr()
1538 cirrus_update_bank_ptr(s, 0); in cirrus_vga_write_gr()
1542 case 0x0B: in cirrus_vga_write_gr()
1544 cirrus_update_bank_ptr(s, 0); in cirrus_vga_write_gr()
1548 case 0x10: // BGCOLOR 0x0000ff00 in cirrus_vga_write_gr()
1549 case 0x11: // FGCOLOR 0x0000ff00 in cirrus_vga_write_gr()
1550 case 0x12: // BGCOLOR 0x00ff0000 in cirrus_vga_write_gr()
1551 case 0x13: // FGCOLOR 0x00ff0000 in cirrus_vga_write_gr()
1552 case 0x14: // BGCOLOR 0xff000000 in cirrus_vga_write_gr()
1553 case 0x15: // FGCOLOR 0xff000000 in cirrus_vga_write_gr()
1554 case 0x20: // BLT WIDTH 0x0000ff in cirrus_vga_write_gr()
1555 case 0x22: // BLT HEIGHT 0x0000ff in cirrus_vga_write_gr()
1556 case 0x24: // BLT DEST PITCH 0x0000ff in cirrus_vga_write_gr()
1557 case 0x26: // BLT SRC PITCH 0x0000ff in cirrus_vga_write_gr()
1558 case 0x28: // BLT DEST ADDR 0x0000ff in cirrus_vga_write_gr()
1559 case 0x29: // BLT DEST ADDR 0x00ff00 in cirrus_vga_write_gr()
1560 case 0x2c: // BLT SRC ADDR 0x0000ff in cirrus_vga_write_gr()
1561 case 0x2d: // BLT SRC ADDR 0x00ff00 in cirrus_vga_write_gr()
1562 case 0x2f: // BLT WRITEMASK in cirrus_vga_write_gr()
1563 case 0x30: // BLT MODE in cirrus_vga_write_gr()
1564 case 0x32: // RASTER OP in cirrus_vga_write_gr()
1565 case 0x33: // BLT MODEEXT in cirrus_vga_write_gr()
1566 case 0x34: // BLT TRANSPARENT COLOR 0x00ff in cirrus_vga_write_gr()
1567 case 0x35: // BLT TRANSPARENT COLOR 0xff00 in cirrus_vga_write_gr()
1568 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff in cirrus_vga_write_gr()
1569 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 in cirrus_vga_write_gr()
1572 case 0x21: // BLT WIDTH 0x001f00 in cirrus_vga_write_gr()
1573 case 0x23: // BLT HEIGHT 0x001f00 in cirrus_vga_write_gr()
1574 case 0x25: // BLT DEST PITCH 0x001f00 in cirrus_vga_write_gr()
1575 case 0x27: // BLT SRC PITCH 0x001f00 in cirrus_vga_write_gr()
1576 s->vga.gr[reg_index] = reg_value & 0x1f; in cirrus_vga_write_gr()
1578 case 0x2a: // BLT DEST ADDR 0x3f0000 in cirrus_vga_write_gr()
1579 s->vga.gr[reg_index] = reg_value & 0x3f; in cirrus_vga_write_gr()
1581 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { in cirrus_vga_write_gr()
1585 case 0x2e: // BLT SRC ADDR 0x3f0000 in cirrus_vga_write_gr()
1586 s->vga.gr[reg_index] = reg_value & 0x3f; in cirrus_vga_write_gr()
1588 case 0x31: // BLT STATUS/START in cirrus_vga_write_gr()
1593 "cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n", in cirrus_vga_write_gr()
1601 * I/O access between 0x3d4-0x3d5
1608 case 0x00: // Standard VGA in cirrus_vga_read_cr()
1609 case 0x01: // Standard VGA in cirrus_vga_read_cr()
1610 case 0x02: // Standard VGA in cirrus_vga_read_cr()
1611 case 0x03: // Standard VGA in cirrus_vga_read_cr()
1612 case 0x04: // Standard VGA in cirrus_vga_read_cr()
1613 case 0x05: // Standard VGA in cirrus_vga_read_cr()
1614 case 0x06: // Standard VGA in cirrus_vga_read_cr()
1615 case 0x07: // Standard VGA in cirrus_vga_read_cr()
1616 case 0x08: // Standard VGA in cirrus_vga_read_cr()
1617 case 0x09: // Standard VGA in cirrus_vga_read_cr()
1618 case 0x0a: // Standard VGA in cirrus_vga_read_cr()
1619 case 0x0b: // Standard VGA in cirrus_vga_read_cr()
1620 case 0x0c: // Standard VGA in cirrus_vga_read_cr()
1621 case 0x0d: // Standard VGA in cirrus_vga_read_cr()
1622 case 0x0e: // Standard VGA in cirrus_vga_read_cr()
1623 case 0x0f: // Standard VGA in cirrus_vga_read_cr()
1624 case 0x10: // Standard VGA in cirrus_vga_read_cr()
1625 case 0x11: // Standard VGA in cirrus_vga_read_cr()
1626 case 0x12: // Standard VGA in cirrus_vga_read_cr()
1627 case 0x13: // Standard VGA in cirrus_vga_read_cr()
1628 case 0x14: // Standard VGA in cirrus_vga_read_cr()
1629 case 0x15: // Standard VGA in cirrus_vga_read_cr()
1630 case 0x16: // Standard VGA in cirrus_vga_read_cr()
1631 case 0x17: // Standard VGA in cirrus_vga_read_cr()
1632 case 0x18: // Standard VGA in cirrus_vga_read_cr()
1634 case 0x24: // Attribute Controller Toggle Readback (R) in cirrus_vga_read_cr()
1636 case 0x19: // Interlace End in cirrus_vga_read_cr()
1637 case 0x1a: // Miscellaneous Control in cirrus_vga_read_cr()
1638 case 0x1b: // Extended Display Control in cirrus_vga_read_cr()
1639 case 0x1c: // Sync Adjust and Genlock in cirrus_vga_read_cr()
1640 case 0x1d: // Overlay Extended Control in cirrus_vga_read_cr()
1641 case 0x22: // Graphics Data Latches Readback (R) in cirrus_vga_read_cr()
1642 case 0x25: // Part Status in cirrus_vga_read_cr()
1643 case 0x27: // Part ID (R) in cirrus_vga_read_cr()
1645 case 0x26: // Attribute Controller Index Readback (R) in cirrus_vga_read_cr()
1646 return s->vga.ar_index & 0x3f; in cirrus_vga_read_cr()
1649 "cirrus: inport cr_index 0x%02x\n", reg_index); in cirrus_vga_read_cr()
1650 return 0xff; in cirrus_vga_read_cr()
1657 case 0x00: // Standard VGA in cirrus_vga_write_cr()
1658 case 0x01: // Standard VGA in cirrus_vga_write_cr()
1659 case 0x02: // Standard VGA in cirrus_vga_write_cr()
1660 case 0x03: // Standard VGA in cirrus_vga_write_cr()
1661 case 0x04: // Standard VGA in cirrus_vga_write_cr()
1662 case 0x05: // Standard VGA in cirrus_vga_write_cr()
1663 case 0x06: // Standard VGA in cirrus_vga_write_cr()
1664 case 0x07: // Standard VGA in cirrus_vga_write_cr()
1665 case 0x08: // Standard VGA in cirrus_vga_write_cr()
1666 case 0x09: // Standard VGA in cirrus_vga_write_cr()
1667 case 0x0a: // Standard VGA in cirrus_vga_write_cr()
1668 case 0x0b: // Standard VGA in cirrus_vga_write_cr()
1669 case 0x0c: // Standard VGA in cirrus_vga_write_cr()
1670 case 0x0d: // Standard VGA in cirrus_vga_write_cr()
1671 case 0x0e: // Standard VGA in cirrus_vga_write_cr()
1672 case 0x0f: // Standard VGA in cirrus_vga_write_cr()
1673 case 0x10: // Standard VGA in cirrus_vga_write_cr()
1674 case 0x11: // Standard VGA in cirrus_vga_write_cr()
1675 case 0x12: // Standard VGA in cirrus_vga_write_cr()
1676 case 0x13: // Standard VGA in cirrus_vga_write_cr()
1677 case 0x14: // Standard VGA in cirrus_vga_write_cr()
1678 case 0x15: // Standard VGA in cirrus_vga_write_cr()
1679 case 0x16: // Standard VGA in cirrus_vga_write_cr()
1680 case 0x17: // Standard VGA in cirrus_vga_write_cr()
1681 case 0x18: // Standard VGA in cirrus_vga_write_cr()
1683 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { in cirrus_vga_write_cr()
1686 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); in cirrus_vga_write_cr()
1691 case 0x00: in cirrus_vga_write_cr()
1692 case 0x04: in cirrus_vga_write_cr()
1693 case 0x05: in cirrus_vga_write_cr()
1694 case 0x06: in cirrus_vga_write_cr()
1695 case 0x07: in cirrus_vga_write_cr()
1696 case 0x11: in cirrus_vga_write_cr()
1697 case 0x17: in cirrus_vga_write_cr()
1702 case 0x19: // Interlace End in cirrus_vga_write_cr()
1703 case 0x1a: // Miscellaneous Control in cirrus_vga_write_cr()
1704 case 0x1b: // Extended Display Control in cirrus_vga_write_cr()
1705 case 0x1c: // Sync Adjust and Genlock in cirrus_vga_write_cr()
1706 case 0x1d: // Overlay Extended Control in cirrus_vga_write_cr()
1713 case 0x22: // Graphics Data Latches Readback (R) in cirrus_vga_write_cr()
1714 case 0x24: // Attribute Controller Toggle Readback (R) in cirrus_vga_write_cr()
1715 case 0x26: // Attribute Controller Index Readback (R) in cirrus_vga_write_cr()
1716 case 0x27: // Part ID (R) in cirrus_vga_write_cr()
1718 case 0x25: // Part Status in cirrus_vga_write_cr()
1721 "cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n", in cirrus_vga_write_cr()
1735 int value = 0xff; in cirrus_mmio_blt_read()
1738 case (CIRRUS_MMIO_BLTBGCOLOR + 0): in cirrus_mmio_blt_read()
1739 value = cirrus_vga_read_gr(s, 0x00); in cirrus_mmio_blt_read()
1742 value = cirrus_vga_read_gr(s, 0x10); in cirrus_mmio_blt_read()
1745 value = cirrus_vga_read_gr(s, 0x12); in cirrus_mmio_blt_read()
1748 value = cirrus_vga_read_gr(s, 0x14); in cirrus_mmio_blt_read()
1750 case (CIRRUS_MMIO_BLTFGCOLOR + 0): in cirrus_mmio_blt_read()
1751 value = cirrus_vga_read_gr(s, 0x01); in cirrus_mmio_blt_read()
1754 value = cirrus_vga_read_gr(s, 0x11); in cirrus_mmio_blt_read()
1757 value = cirrus_vga_read_gr(s, 0x13); in cirrus_mmio_blt_read()
1760 value = cirrus_vga_read_gr(s, 0x15); in cirrus_mmio_blt_read()
1762 case (CIRRUS_MMIO_BLTWIDTH + 0): in cirrus_mmio_blt_read()
1763 value = cirrus_vga_read_gr(s, 0x20); in cirrus_mmio_blt_read()
1766 value = cirrus_vga_read_gr(s, 0x21); in cirrus_mmio_blt_read()
1768 case (CIRRUS_MMIO_BLTHEIGHT + 0): in cirrus_mmio_blt_read()
1769 value = cirrus_vga_read_gr(s, 0x22); in cirrus_mmio_blt_read()
1772 value = cirrus_vga_read_gr(s, 0x23); in cirrus_mmio_blt_read()
1774 case (CIRRUS_MMIO_BLTDESTPITCH + 0): in cirrus_mmio_blt_read()
1775 value = cirrus_vga_read_gr(s, 0x24); in cirrus_mmio_blt_read()
1778 value = cirrus_vga_read_gr(s, 0x25); in cirrus_mmio_blt_read()
1780 case (CIRRUS_MMIO_BLTSRCPITCH + 0): in cirrus_mmio_blt_read()
1781 value = cirrus_vga_read_gr(s, 0x26); in cirrus_mmio_blt_read()
1784 value = cirrus_vga_read_gr(s, 0x27); in cirrus_mmio_blt_read()
1786 case (CIRRUS_MMIO_BLTDESTADDR + 0): in cirrus_mmio_blt_read()
1787 value = cirrus_vga_read_gr(s, 0x28); in cirrus_mmio_blt_read()
1790 value = cirrus_vga_read_gr(s, 0x29); in cirrus_mmio_blt_read()
1793 value = cirrus_vga_read_gr(s, 0x2a); in cirrus_mmio_blt_read()
1795 case (CIRRUS_MMIO_BLTSRCADDR + 0): in cirrus_mmio_blt_read()
1796 value = cirrus_vga_read_gr(s, 0x2c); in cirrus_mmio_blt_read()
1799 value = cirrus_vga_read_gr(s, 0x2d); in cirrus_mmio_blt_read()
1802 value = cirrus_vga_read_gr(s, 0x2e); in cirrus_mmio_blt_read()
1805 value = cirrus_vga_read_gr(s, 0x2f); in cirrus_mmio_blt_read()
1808 value = cirrus_vga_read_gr(s, 0x30); in cirrus_mmio_blt_read()
1811 value = cirrus_vga_read_gr(s, 0x32); in cirrus_mmio_blt_read()
1814 value = cirrus_vga_read_gr(s, 0x33); in cirrus_mmio_blt_read()
1816 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): in cirrus_mmio_blt_read()
1817 value = cirrus_vga_read_gr(s, 0x34); in cirrus_mmio_blt_read()
1820 value = cirrus_vga_read_gr(s, 0x35); in cirrus_mmio_blt_read()
1822 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): in cirrus_mmio_blt_read()
1823 value = cirrus_vga_read_gr(s, 0x38); in cirrus_mmio_blt_read()
1826 value = cirrus_vga_read_gr(s, 0x39); in cirrus_mmio_blt_read()
1829 value = cirrus_vga_read_gr(s, 0x31); in cirrus_mmio_blt_read()
1833 "cirrus: mmio read - address 0x%04x\n", address); in cirrus_mmio_blt_read()
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 0): in cirrus_mmio_blt_write()
1847 cirrus_vga_write_gr(s, 0x00, value); in cirrus_mmio_blt_write()
1850 cirrus_vga_write_gr(s, 0x10, value); in cirrus_mmio_blt_write()
1853 cirrus_vga_write_gr(s, 0x12, value); in cirrus_mmio_blt_write()
1856 cirrus_vga_write_gr(s, 0x14, value); in cirrus_mmio_blt_write()
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 0): in cirrus_mmio_blt_write()
1859 cirrus_vga_write_gr(s, 0x01, value); in cirrus_mmio_blt_write()
1862 cirrus_vga_write_gr(s, 0x11, value); in cirrus_mmio_blt_write()
1865 cirrus_vga_write_gr(s, 0x13, value); in cirrus_mmio_blt_write()
1868 cirrus_vga_write_gr(s, 0x15, value); in cirrus_mmio_blt_write()
1870 case (CIRRUS_MMIO_BLTWIDTH + 0): in cirrus_mmio_blt_write()
1871 cirrus_vga_write_gr(s, 0x20, value); in cirrus_mmio_blt_write()
1874 cirrus_vga_write_gr(s, 0x21, value); in cirrus_mmio_blt_write()
1876 case (CIRRUS_MMIO_BLTHEIGHT + 0): in cirrus_mmio_blt_write()
1877 cirrus_vga_write_gr(s, 0x22, value); in cirrus_mmio_blt_write()
1880 cirrus_vga_write_gr(s, 0x23, value); in cirrus_mmio_blt_write()
1882 case (CIRRUS_MMIO_BLTDESTPITCH + 0): in cirrus_mmio_blt_write()
1883 cirrus_vga_write_gr(s, 0x24, value); in cirrus_mmio_blt_write()
1886 cirrus_vga_write_gr(s, 0x25, value); in cirrus_mmio_blt_write()
1888 case (CIRRUS_MMIO_BLTSRCPITCH + 0): in cirrus_mmio_blt_write()
1889 cirrus_vga_write_gr(s, 0x26, value); in cirrus_mmio_blt_write()
1892 cirrus_vga_write_gr(s, 0x27, value); in cirrus_mmio_blt_write()
1894 case (CIRRUS_MMIO_BLTDESTADDR + 0): in cirrus_mmio_blt_write()
1895 cirrus_vga_write_gr(s, 0x28, value); in cirrus_mmio_blt_write()
1898 cirrus_vga_write_gr(s, 0x29, value); in cirrus_mmio_blt_write()
1901 cirrus_vga_write_gr(s, 0x2a, value); in cirrus_mmio_blt_write()
1906 case (CIRRUS_MMIO_BLTSRCADDR + 0): in cirrus_mmio_blt_write()
1907 cirrus_vga_write_gr(s, 0x2c, value); in cirrus_mmio_blt_write()
1910 cirrus_vga_write_gr(s, 0x2d, value); in cirrus_mmio_blt_write()
1913 cirrus_vga_write_gr(s, 0x2e, value); in cirrus_mmio_blt_write()
1916 cirrus_vga_write_gr(s, 0x2f, value); in cirrus_mmio_blt_write()
1919 cirrus_vga_write_gr(s, 0x30, value); in cirrus_mmio_blt_write()
1922 cirrus_vga_write_gr(s, 0x32, value); in cirrus_mmio_blt_write()
1925 cirrus_vga_write_gr(s, 0x33, value); in cirrus_mmio_blt_write()
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): in cirrus_mmio_blt_write()
1928 cirrus_vga_write_gr(s, 0x34, value); in cirrus_mmio_blt_write()
1931 cirrus_vga_write_gr(s, 0x35, value); in cirrus_mmio_blt_write()
1933 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): in cirrus_mmio_blt_write()
1934 cirrus_vga_write_gr(s, 0x38, value); in cirrus_mmio_blt_write()
1937 cirrus_vga_write_gr(s, 0x39, value); in cirrus_mmio_blt_write()
1940 cirrus_vga_write_gr(s, 0x31, value); in cirrus_mmio_blt_write()
1944 "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", in cirrus_mmio_blt_write()
1965 for (x = 0; x < 8; x++) { in cirrus_mem_writeb_mode4and5_8bpp()
1967 if (val & 0x80) { in cirrus_mem_writeb_mode4and5_8bpp()
1986 for (x = 0; x < 8; x++) { in cirrus_mem_writeb_mode4and5_16bpp()
1988 if (val & 0x80) { in cirrus_mem_writeb_mode4and5_16bpp()
1990 *(dst + 1) = s->vga.gr[0x11]; in cirrus_mem_writeb_mode4and5_16bpp()
1993 *(dst + 1) = s->vga.gr[0x10]; in cirrus_mem_writeb_mode4and5_16bpp()
2002 * memory access between 0xa0000-0xbffff
2015 if ((s->vga.sr[0x07] & 0x01) == 0) { in cirrus_vga_mem_read()
2019 if (addr < 0x10000) { in cirrus_vga_mem_read()
2023 bank_offset = addr & 0x7fff; in cirrus_vga_mem_read()
2026 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_vga_mem_read()
2028 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_vga_mem_read()
2034 val = 0xff; in cirrus_vga_mem_read()
2035 } else if (addr >= 0x18000 && addr < 0x18100) { in cirrus_vga_mem_read()
2037 val = 0xff; in cirrus_vga_mem_read()
2038 if ((s->vga.sr[0x17] & 0x44) == 0x04) { in cirrus_vga_mem_read()
2039 val = cirrus_mmio_blt_read(s, addr & 0xff); in cirrus_vga_mem_read()
2042 val = 0xff; in cirrus_vga_mem_read()
2044 "cirrus: mem_readb 0x" HWADDR_FMT_plx "\n", addr); in cirrus_vga_mem_read()
2059 if ((s->vga.sr[0x07] & 0x01) == 0) { in cirrus_vga_mem_write()
2064 if (addr < 0x10000) { in cirrus_vga_mem_write()
2074 bank_offset = addr & 0x7fff; in cirrus_vga_mem_write()
2077 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_vga_mem_write()
2079 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_vga_mem_write()
2083 mode = s->vga.gr[0x05] & 0x7; in cirrus_vga_mem_write()
2084 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_vga_mem_write()
2089 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { in cirrus_vga_mem_write()
2101 } else if (addr >= 0x18000 && addr < 0x18100) { in cirrus_vga_mem_write()
2103 if ((s->vga.sr[0x17] & 0x44) == 0x04) { in cirrus_vga_mem_write()
2104 cirrus_mmio_blt_write(s, addr & 0xff, mem_value); in cirrus_vga_mem_write()
2108 "cirrus: mem_writeb 0x" HWADDR_FMT_plx " " in cirrus_vga_mem_write()
2109 "value 0x%02" PRIx64 "\n", addr, mem_value); in cirrus_vga_mem_write()
2145 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_compute_yrange()
2146 src += (s->vga.sr[0x13] & 0x3c) * 256; in cirrus_cursor_compute_yrange()
2149 for(y = 0; y < 64; y++) { in cirrus_cursor_compute_yrange()
2150 content = ((uint32_t *)src)[0] | in cirrus_cursor_compute_yrange()
2163 src += (s->vga.sr[0x13] & 0x3f) * 256; in cirrus_cursor_compute_yrange()
2166 for(y = 0; y < 32; y++) { in cirrus_cursor_compute_yrange()
2167 content = ((uint32_t *)src)[0] | in cirrus_cursor_compute_yrange()
2168 ((uint32_t *)(src + 128))[0]; in cirrus_cursor_compute_yrange()
2179 s->last_hw_cursor_y_start = 0; in cirrus_cursor_compute_yrange()
2180 s->last_hw_cursor_y_end = 0; in cirrus_cursor_compute_yrange()
2194 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { in cirrus_cursor_invalidate()
2195 size = 0; in cirrus_cursor_invalidate()
2197 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) in cirrus_cursor_invalidate()
2232 for (x = 0; x < w; x++) { in vga_draw_cursor_line()
2236 case 0: in vga_draw_cursor_line()
2239 ((uint32_t *)d)[0] ^= color_xor; in vga_draw_cursor_line()
2242 ((uint32_t *)d)[0] = color0; in vga_draw_cursor_line()
2245 ((uint32_t *)d)[0] = color1; in vga_draw_cursor_line()
2260 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) in cirrus_cursor_draw_line()
2263 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_draw_line()
2274 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_draw_line()
2275 src += (s->vga.sr[0x13] & 0x3c) * 256; in cirrus_cursor_draw_line()
2278 content = ((uint32_t *)src)[0] | in cirrus_cursor_draw_line()
2283 src += (s->vga.sr[0x13] & 0x3f) * 256; in cirrus_cursor_draw_line()
2288 content = ((uint32_t *)src)[0] | in cirrus_cursor_draw_line()
2289 ((uint32_t *)(src + 128))[0]; in cirrus_cursor_draw_line()
2304 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]), in cirrus_cursor_draw_line()
2305 c6_to_8(palette[0x0 * 3 + 1]), in cirrus_cursor_draw_line()
2306 c6_to_8(palette[0x0 * 3 + 2])); in cirrus_cursor_draw_line()
2307 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]), in cirrus_cursor_draw_line()
2308 c6_to_8(palette[0xf * 3 + 1]), in cirrus_cursor_draw_line()
2309 c6_to_8(palette[0xf * 3 + 2])); in cirrus_cursor_draw_line()
2311 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff); in cirrus_cursor_draw_line()
2328 if (((s->vga.sr[0x17] & 0x44) == 0x44) && in cirrus_linear_read()
2331 ret = cirrus_mmio_blt_read(s, addr & 0xff); in cirrus_linear_read()
2332 } else if (0) { in cirrus_linear_read()
2334 ret = 0xff; in cirrus_linear_read()
2337 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_linear_read()
2339 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_linear_read()
2357 if (((s->vga.sr[0x17] & 0x44) == 0x44) && in cirrus_linear_write()
2360 cirrus_mmio_blt_write(s, addr & 0xff, val); in cirrus_linear_write()
2369 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_linear_write()
2371 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_linear_write()
2376 mode = s->vga.gr[0x05] & 0x7; in cirrus_linear_write()
2377 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_linear_write()
2381 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { in cirrus_linear_write()
2408 return 0xff; in cirrus_linear_bitblt_read()
2441 && !((s->vga.sr[0x07] & 0x01) == 0) in map_linear_vram_bank()
2442 && !((s->vga.gr[0x0B] & 0x14) == 0x14) in map_linear_vram_bank()
2443 && !(s->vga.gr[0x0B] & 0x02); in map_linear_vram_bank()
2453 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); in map_linear_vram()
2455 map_linear_vram_bank(s, 0); in map_linear_vram()
2465 memory_region_set_enabled(&s->cirrus_bank[0], false); in unmap_linear_vram()
2475 if ((s->vga.sr[0x17] & 0x44) == 0x44) { in cirrus_update_memory_access()
2480 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_update_memory_access()
2482 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_update_memory_access()
2486 mode = s->vga.gr[0x05] & 0x7; in cirrus_update_memory_access()
2487 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_update_memory_access()
2507 addr += 0x3b0; in cirrus_vga_ioport_read()
2510 val = 0xff; in cirrus_vga_ioport_read()
2513 case 0x3c0: in cirrus_vga_ioport_read()
2514 if (s->ar_flip_flop == 0) { in cirrus_vga_ioport_read()
2517 val = 0; in cirrus_vga_ioport_read()
2520 case 0x3c1: in cirrus_vga_ioport_read()
2521 index = s->ar_index & 0x1f; in cirrus_vga_ioport_read()
2525 val = 0; in cirrus_vga_ioport_read()
2527 case 0x3c2: in cirrus_vga_ioport_read()
2530 case 0x3c4: in cirrus_vga_ioport_read()
2533 case 0x3c5: in cirrus_vga_ioport_read()
2537 case 0x3c6: in cirrus_vga_ioport_read()
2540 case 0x3c7: in cirrus_vga_ioport_read()
2543 case 0x3c8: in cirrus_vga_ioport_read()
2545 c->cirrus_hidden_dac_lockindex = 0; in cirrus_vga_ioport_read()
2547 case 0x3c9: in cirrus_vga_ioport_read()
2550 case 0x3ca: in cirrus_vga_ioport_read()
2553 case 0x3cc: in cirrus_vga_ioport_read()
2556 case 0x3ce: in cirrus_vga_ioport_read()
2559 case 0x3cf: in cirrus_vga_ioport_read()
2562 case 0x3b4: in cirrus_vga_ioport_read()
2563 case 0x3d4: in cirrus_vga_ioport_read()
2566 case 0x3b5: in cirrus_vga_ioport_read()
2567 case 0x3d5: in cirrus_vga_ioport_read()
2570 case 0x3ba: in cirrus_vga_ioport_read()
2571 case 0x3da: in cirrus_vga_ioport_read()
2574 s->ar_flip_flop = 0; in cirrus_vga_ioport_read()
2577 val = 0x00; in cirrus_vga_ioport_read()
2592 addr += 0x3b0; in cirrus_vga_ioport_write()
2601 case 0x3c0: in cirrus_vga_ioport_write()
2602 if (s->ar_flip_flop == 0) { in cirrus_vga_ioport_write()
2603 val &= 0x3f; in cirrus_vga_ioport_write()
2606 index = s->ar_index & 0x1f; in cirrus_vga_ioport_write()
2608 case 0x00 ... 0x0f: in cirrus_vga_ioport_write()
2609 s->ar[index] = val & 0x3f; in cirrus_vga_ioport_write()
2611 case 0x10: in cirrus_vga_ioport_write()
2612 s->ar[index] = val & ~0x10; in cirrus_vga_ioport_write()
2614 case 0x11: in cirrus_vga_ioport_write()
2617 case 0x12: in cirrus_vga_ioport_write()
2618 s->ar[index] = val & ~0xc0; in cirrus_vga_ioport_write()
2620 case 0x13: in cirrus_vga_ioport_write()
2621 s->ar[index] = val & ~0xf0; in cirrus_vga_ioport_write()
2623 case 0x14: in cirrus_vga_ioport_write()
2624 s->ar[index] = val & ~0xf0; in cirrus_vga_ioport_write()
2632 case 0x3c2: in cirrus_vga_ioport_write()
2633 s->msr = val & ~0x10; in cirrus_vga_ioport_write()
2636 case 0x3c4: in cirrus_vga_ioport_write()
2639 case 0x3c5: in cirrus_vga_ioport_write()
2642 case 0x3c6: in cirrus_vga_ioport_write()
2645 case 0x3c7: in cirrus_vga_ioport_write()
2647 s->dac_sub_index = 0; in cirrus_vga_ioport_write()
2650 case 0x3c8: in cirrus_vga_ioport_write()
2652 s->dac_sub_index = 0; in cirrus_vga_ioport_write()
2653 s->dac_state = 0; in cirrus_vga_ioport_write()
2655 case 0x3c9: in cirrus_vga_ioport_write()
2658 case 0x3ce: in cirrus_vga_ioport_write()
2661 case 0x3cf: in cirrus_vga_ioport_write()
2664 case 0x3b4: in cirrus_vga_ioport_write()
2665 case 0x3d4: in cirrus_vga_ioport_write()
2668 case 0x3b5: in cirrus_vga_ioport_write()
2669 case 0x3d5: in cirrus_vga_ioport_write()
2672 case 0x3ba: in cirrus_vga_ioport_write()
2673 case 0x3da: in cirrus_vga_ioport_write()
2674 s->fcr = val & 0x10; in cirrus_vga_ioport_write()
2690 if (addr >= 0x100) { in cirrus_mmio_read()
2691 return cirrus_mmio_blt_read(s, addr - 0x100); in cirrus_mmio_read()
2693 return cirrus_vga_ioport_read(s, addr + 0x10, size); in cirrus_mmio_read()
2702 if (addr >= 0x100) { in cirrus_mmio_write()
2703 cirrus_mmio_blt_write(s, addr - 0x100, val); in cirrus_mmio_write()
2705 cirrus_vga_ioport_write(s, addr + 0x10, val, size); in cirrus_mmio_write()
2725 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; in cirrus_post_load()
2726 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; in cirrus_post_load()
2728 cirrus_update_bank_ptr(s, 0); in cirrus_post_load()
2734 return 0; in cirrus_post_load()
2782 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2800 s->vga.sr[0x06] = 0x0f; in cirrus_reset()
2803 s->vga.sr[0x1F] = 0x2d; // MemClock in cirrus_reset()
2804 s->vga.gr[0x18] = 0x0f; // fastest memory configuration in cirrus_reset()
2805 s->vga.sr[0x0f] = 0x98; in cirrus_reset()
2806 s->vga.sr[0x17] = 0x20; in cirrus_reset()
2807 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ in cirrus_reset()
2809 s->vga.sr[0x1F] = 0x22; // MemClock in cirrus_reset()
2810 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M; in cirrus_reset()
2811 s->vga.sr[0x17] = s->bustype; in cirrus_reset()
2812 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ in cirrus_reset()
2814 s->vga.cr[0x27] = s->device_id; in cirrus_reset()
2817 s->cirrus_hidden_dac_data = 0; in cirrus_reset()
2849 for(i = 0;i < 256; i++) in cirrus_init_common()
2851 rop_to_index[CIRRUS_ROP_0] = 0; in cirrus_init_common()
2874 /* Register ioport 0x3b0 - 0x3df */ in cirrus_init_common()
2876 "cirrus-io", 0x30); in cirrus_init_common()
2878 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io); in cirrus_init_common()
2882 0x20000); in cirrus_init_common()
2885 "cirrus-low-memory", 0x20000); in cirrus_init_common()
2886 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem); in cirrus_init_common()
2887 for (i = 0; i < 2; ++i) { in cirrus_init_common()
2891 0, 0x8000); in cirrus_init_common()
2893 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000, in cirrus_init_common()
2897 0x000a0000, in cirrus_init_common()
2912 0x400000); in cirrus_init_common()
2965 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga); in pci_cirrus_vga_realize()
2968 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000); in pci_cirrus_vga_realize()
2971 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io); in pci_cirrus_vga_realize()
2972 memory_region_add_subregion(&s->pci_bar, 0x1000000, in pci_cirrus_vga_realize()
2976 /* memory #0 LFB */ in pci_cirrus_vga_realize()
2979 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar); in pci_cirrus_vga_realize()
2981 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); in pci_cirrus_vga_realize()