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/qemu/target/ppc/translate/
H A Dfp-ops.c.inc2 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
4 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
5 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
6 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
7 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
8 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
11 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
12 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
[all …]
H A Dspe-ops.c.inc1 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
2 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
3 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
4 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
8 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
12 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
[all …]
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
/qemu/tests/unit/
H A Dtest-crypto-afsplit.c43 "\x00\x01\x02\x03\x04\x05\x06\x07"
75 "\x00\x01\x02\x03\x04\x05\x06\x07"
84 "\x00\x01\x02\x03\x04\x05\x06\x07"
95 "\x00\x01\x02\x03\x04\x05\x06\x07"
97 "\x00\x01\x02\x03\x04\x05\x06\x07"
99 "\x00\x01\x02\x03\x04\x05\x06\x07"
101 "\x00\x01\x02\x03\x04\x05\x06\x07"
110 return '0' + i; in hex()
121 for (i = 0; i < len; i++) { in hex_string()
122 hexstr[i * 2] = hex((bytes[i] >> 4) & 0xf); in hex_string()
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
47 "\x21\xcb\x04\xda\xfb\x1e\x35\x92\xcd\x69\xc0\x83\x06\x83\x8e\x39"
53 "\x64\x06\x0e\xef\xe0\x6a\x5e\x6a\x41\x42\x96\x6d\xb8\x7d\xea\x95"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
68 "\xa3\xfc\x33\x55\x89\xa9\xc3\xea\x5b\x2e\x31\x06\xf8\xcb\x9e\x6e"
114 "\x9e\x48\x36\x62\x0b\x05\xfa\x38\xc1\x06\x04\x58\x95\x4d\x25\x13"
126 "\xcf\x05\x88\x25\x90\x79\x18\xc0\x01\x06\x42\x8e\x48\x50\x27\xf0"
133 "\x05\x63\x01\x6d\x77\x06\x71\x24\xcf\x32\x01\xe2\x51\xed\x5e\x90"
144 "\x24\xa1\xad\x13\x35\x31\xc0\x0b\xf1\xd2\x06\x7c\x94\x1a\x21\x2f"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
[all …]
H A Dtest-crypto-ivgen.c40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
85 .sector = 0x1f2e3d4c5b6a7988ULL,
94 .sector = 0x1,
98 .key = (const uint8_t *)"\x00\x01\x02\x03\x04\x05\x06\x07"
108 .sector = 0x1f2e3d4cULL,
112 .key = (const uint8_t *)"\x00\x01\x02\x03\x04\x05\x06\x07"
[all …]
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/qemu/linux-user/arm/
H A Dvdso.S20 .eabi_attribute Tag_FP_arch, 0
21 .eabi_attribute Tag_ARM_ISA_use, 0
26 .ifne \n < 0x100
28 .elseif \n < 0x1ff
29 mov r7, #0xff
30 add r7, #(\n - 0xff)
34 swi #0
98 .cfi_escape 0x10, 9, 7, 0x7d, (\ofs & 0x7f) + 0x80, (\ofs >> 7), 0x06, 0x23, 4, 0x06
109 .cfi_escape 0x10, 14, 5, 0x7d, (\ofs & 0x7f) + 0x80, (\ofs >> 7), 0x06, 0x06
144 slot 0
/qemu/pc-bios/keymaps/
H A Dsl3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
/qemu/tests/qtest/
H A Dfuzz-sdcard-test.c24 " -drive if=none,index=0,file=null-co://,format=raw,id=d0"); in oss_fuzz_29225()
26 qtest_outl(s, 0xcf8, 0x80001010); in oss_fuzz_29225()
27 qtest_outl(s, 0xcfc, 0xd0690); in oss_fuzz_29225()
28 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
29 qtest_outl(s, 0xcf8, 0x80001013); in oss_fuzz_29225()
30 qtest_outl(s, 0xcfc, 0xffffffff); in oss_fuzz_29225()
31 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
32 qtest_outl(s, 0xcfc, 0x3effe00); in oss_fuzz_29225()
34 qtest_bufwrite(s, 0xff0d062c, "\xff", 0x1); in oss_fuzz_29225()
35 qtest_bufwrite(s, 0xff0d060f, "\xb7", 0x1); in oss_fuzz_29225()
[all …]
H A Dboot-serial-test.c21 0x88, 0xe0, /* ldi r24, 0x08 */
22 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
23 0x86, 0xe0, /* ldi r24, 0x06 */
24 0x80, 0x93, 0xc2, 0x00, /* sts 0x00C2, r24 ; Set the data bits to 8 */
25 0x84, 0xe5, /* ldi r24, 0x54 */
26 0x80, 0x93, 0xc6, 0x00, /* sts 0x00C6, r24 ; Output 'T' */
30 0x0c, 0xc0, 0x3f, 0x14, /* lu12i.w $t0, 0x1fe00 */
31 0x8c, 0x81, 0x87, 0x03, /* ori $t0, $t0, 0x1e0 */
32 0x0d, 0x50, 0x81, 0x03, /* li.w $t1, 'T' */
33 0x8d, 0x01, 0x00, 0x29, /* st.b $t1, $t0, 0 */
[all …]
H A Dfuzz-lsi53c895a-test.c25 qtest_outl(s, 0xcf8, 0x80000804); /* PCI Command Register */ in test_lsi_dma_reentrancy()
26 qtest_outw(s, 0xcfc, 0x7); /* Enables accesses */ in test_lsi_dma_reentrancy()
27 qtest_outl(s, 0xcf8, 0x80000814); /* Memory Bar 1 */ in test_lsi_dma_reentrancy()
28 qtest_outl(s, 0xcfc, 0xff100000); /* Set MMIO Address*/ in test_lsi_dma_reentrancy()
29 qtest_outl(s, 0xcf8, 0x80000818); /* Memory Bar 2 */ in test_lsi_dma_reentrancy()
30 qtest_outl(s, 0xcfc, 0xff000000); /* Set RAM Address*/ in test_lsi_dma_reentrancy()
31 qtest_writel(s, 0xff000000, 0xc0000024); in test_lsi_dma_reentrancy()
32 qtest_writel(s, 0xff000114, 0x00000080); in test_lsi_dma_reentrancy()
33 qtest_writel(s, 0xff00012c, 0xff000000); in test_lsi_dma_reentrancy()
34 qtest_writel(s, 0xff000004, 0xff000114); in test_lsi_dma_reentrancy()
[all …]
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py249 address = 0xF0000
50 mem = bits.memory(0xF0000, 0x10000)
51 for offset in range(0, len(mem), 16):
55 csum = sum(map(ord, mem[offset:offset + entry_point_length])) & 0xff
56 if csum == 0:
66 sm._header_memory = bits.memory(sm_ptr, 0x1f)
161 if i == 0:
170 smbios_structure_type = 0
186 characteristic_bytes = self.length - 0x12
211 if self.length > 0x8:
[all …]
/qemu/target/tricore/
H A Dtricore-opcodes.h34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
290 OPCM_16_SR_SYSTEM = 0x00,
291 OPCM_16_SR_ACCU = 0x32,
293 OPC1_16_SRC_ADD = 0xc2,
294 OPC1_16_SRC_ADD_A15 = 0x92,
295 OPC1_16_SRC_ADD_15A = 0x9a,
296 OPC1_16_SRR_ADD = 0x42,
297 OPC1_16_SRR_ADD_A15 = 0x12,
298 OPC1_16_SRR_ADD_15A = 0x1a,
299 OPC1_16_SRC_ADD_A = 0xb0,
[all …]
/qemu/include/hw/display/
H A Ddpcd.h34 #define DPCD_REVISION 0x00
35 #define DPCD_REV_1_0 0x10
36 #define DPCD_REV_1_1 0x11
39 #define DPCD_MAX_LINK_RATE 0x01
40 #define DPCD_1_62GBPS 0x06
41 #define DPCD_2_7GBPS 0x0A
42 #define DPCD_5_4GBPS 0x14
44 #define DPCD_MAX_LANE_COUNT 0x02
45 #define DPCD_ONE_LANE 0x01
46 #define DPCD_TWO_LANES 0x02
[all …]
/qemu/hw/block/
H A Dm25p80_sfdp.c25 0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
26 0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
27 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
28 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
29 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
30 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
31 0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
32 0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
33 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
34 0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
[all …]
/qemu/ui/
H A Dvgafont.h3 /* 0 0x00 '^@' */
4 0x00, /* 00000000 */
5 0x00, /* 00000000 */
6 0x00, /* 00000000 */
7 0x00, /* 00000000 */
8 0x00, /* 00000000 */
9 0x00, /* 00000000 */
10 0x00, /* 00000000 */
11 0x00, /* 00000000 */
12 0x00, /* 00000000 */
[all …]
/qemu/include/hw/scsi/
H A Desp.h83 #define ESP_TCLO 0x0
84 #define ESP_TCMID 0x1
85 #define ESP_FIFO 0x2
86 #define ESP_CMD 0x3
87 #define ESP_RSTAT 0x4
88 #define ESP_WBUSID 0x4
89 #define ESP_RINTR 0x5
90 #define ESP_WSEL 0x5
91 #define ESP_RSEQ 0x6
92 #define ESP_WSYNTP 0x6
[all …]
/qemu/tests/qtest/migration/i386/
H A Da-b-bootblock.h7 0xfa, 0x0f, 0x01, 0x16, 0xb8, 0x7c, 0x66, 0xb8, 0x01, 0x00, 0x00, 0x00,
8 0x0f, 0x22, 0xc0, 0x66, 0xea, 0x20, 0x7c, 0x00, 0x00, 0x08, 0x00, 0x00,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x92, 0x0c, 0x02,
10 0xe6, 0x92, 0xb8, 0x10, 0x00, 0x00, 0x00, 0x8e, 0xd8, 0x66, 0xb8, 0x41,
11 0x00, 0x66, 0xba, 0xf8, 0x03, 0xee, 0xb3, 0x00, 0xb8, 0x00, 0x00, 0x10,
12 0x00, 0xc6, 0x00, 0x00, 0x05, 0x00, 0x10, 0x00, 0x00, 0x3d, 0x00, 0x00,
13 0x40, 0x06, 0x7c, 0xf1, 0xb8, 0x00, 0x00, 0x10, 0x00, 0xfe, 0x00, 0x05,
14 0x00, 0x10, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x40, 0x06, 0x7c, 0xf2, 0xfe,
15 0xc3, 0x80, 0xe3, 0x3f, 0x75, 0xe6, 0x66, 0xb8, 0x42, 0x00, 0x66, 0xba,
16 0xf8, 0x03, 0xee, 0xa1, 0xbe, 0x7c, 0x00, 0x00, 0x83, 0xf8, 0x00, 0x74,
[all …]
/qemu/tests/qtest/migration/s390x/
H A Da-b-bios.h7 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x16, 0x00, 0x00, 0x00, 0x01,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa8, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x80,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x07, 0x00, 0x40,
12 0x00, 0x0d, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
[all …]
/qemu/include/scsi/
H A Dconstants.h30 #define TEST_UNIT_READY 0x00
31 #define REWIND 0x01
32 #define REQUEST_SENSE 0x03
33 #define FORMAT_UNIT 0x04
34 #define READ_BLOCK_LIMITS 0x05
35 #define INITIALIZE_ELEMENT_STATUS 0x07
36 #define REASSIGN_BLOCKS 0x07
37 #define READ_6 0x08
38 #define WRITE_6 0x0a
39 #define SET_CAPACITY 0x0b
[all …]
/qemu/hw/display/
H A Dvga_regs.h32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
38 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
39 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
40 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
41 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
[all …]
/qemu/include/hw/sensor/
H A Demc141x_regs.h15 #define EMC1413_DEVICE_ID 0x21
16 #define EMC1414_DEVICE_ID 0x25
17 #define MANUFACTURER_ID 0x5d
18 #define REVISION 0x04
21 #define EMC141X_TEMP_HIGH0 0x00
22 #define EMC141X_TEMP_HIGH1 0x01
23 #define EMC141X_TEMP_HIGH2 0x23
24 #define EMC141X_TEMP_HIGH3 0x2a
25 #define EMC141X_TEMP_MAX_HIGH0 0x05
26 #define EMC141X_TEMP_MIN_HIGH0 0x06
[all …]
/qemu/linux-user/ppc/
H A Dvdso.S30 addi 0, 0, \nr
91 .cfi_offset 0, 0 * sizeof_reg
173 * DW_OP_plus_uconst (0x23), vreg_ptr, DW_OP_deref (0x06),
174 * DW_OP_plus_uconst (0x23), ofs
176 …i_escape 0x10, 77 + \reg, 7, 0x23, (offsetof_mcontext_vregs_ptr & 0x7f) + 0x80, offsetof_mcontext_…
186 save_vreg 0

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