Lines Matching +full:0 +full:x06
34 #define DPCD_REVISION 0x00
35 #define DPCD_REV_1_0 0x10
36 #define DPCD_REV_1_1 0x11
39 #define DPCD_MAX_LINK_RATE 0x01
40 #define DPCD_1_62GBPS 0x06
41 #define DPCD_2_7GBPS 0x0A
42 #define DPCD_5_4GBPS 0x14
44 #define DPCD_MAX_LANE_COUNT 0x02
45 #define DPCD_ONE_LANE 0x01
46 #define DPCD_TWO_LANES 0x02
47 #define DPCD_FOUR_LANES 0x04
50 #define DPCD_UP_TO_0_5 0x01
51 #define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
54 #define DPCD_DISPLAY_PORT 0x00
55 #define DPCD_ANALOG 0x02
56 #define DPCD_DVI_HDMI 0x04
57 #define DPCD_OTHER 0x06
60 #define DPCD_FORMAT_CONVERSION 0x08
63 #define DPCD_ANSI_8B_10B 0x01
66 #define DPCD_OUI_SUPPORTED 0x80
69 #define DPCD_RECEIVE_PORT0_CAP_0 0x08
70 #define DPCD_RECEIVE_PORT0_CAP_1 0x09
71 #define DPCD_EDID_PRESENT 0x02
72 #define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
75 #define DPCD_CAP_DISPLAY_PORT 0x000
76 #define DPCD_CAP_ANALOG_VGA 0x001
77 #define DPCD_CAP_DVI 0x002
78 #define DPCD_CAP_HDMI 0x003
79 #define DPCD_CAP_OTHER 0x100
81 #define DPCD_LANE0_1_STATUS 0x202
82 #define DPCD_LANE0_CR_DONE (1 << 0)
89 #define DPCD_LANE2_3_STATUS 0x203
90 #define DPCD_LANE2_CR_DONE (1 << 0)
97 #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
98 #define DPCD_INTERLANE_ALIGN_DONE 0x01
99 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED 0x40
100 #define DPCD_LINK_STATUS_UPDATED 0x80
102 #define DPCD_SINK_STATUS 0x205
103 #define DPCD_RECEIVE_PORT_0_STATUS 0x01