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/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux-5.10/drivers/irqchip/
Dirq-st.c18 #define STIH415_SYSCFG_642 0x0a8
19 #define STIH416_SYSCFG_7543 0x87c
20 #define STIH407_SYSCFG_5102 0x198
21 #define STID127_SYSCFG_734 0x088
23 #define ST_A9_IRQ_MASK 0x001FFFFF
26 #define ST_A9_IRQ_EN_CTI_0 BIT(0)
98 return 0; in st_irq_xlate()
109 return 0; in st_irq_xlate()
131 for (i = 0; i < ST_A9_IRQ_MAX_CHANS; i++) { in st_irq_syscfg_enable()
/linux-5.10/fs/xfs/libxfs/
Dxfs_types.h61 #define MAXEXTLEN ((xfs_extlen_t)0x001fffff) /* 21 bits */
62 #define MAXEXTNUM ((xfs_extnum_t)0x7fffffff) /* signed int */
63 #define MAXAEXTNUM ((xfs_aextnum_t)0x7fff) /* signed short */
85 #define XFS_DATA_FORK 0
172 XFS_AG_RESV_NONE = 0,
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dvolt.c32 u32 volt = 0; in nvbios_volt_table()
36 volt = nvbios_rd32(bios, bit_P.offset + 0x0c); in nvbios_volt_table()
39 volt = nvbios_rd32(bios, bit_P.offset + 0x10); in nvbios_volt_table()
42 *ver = nvbios_rd08(bios, volt + 0); in nvbios_volt_table()
44 case 0x12: in nvbios_volt_table()
49 case 0x20: in nvbios_volt_table()
54 case 0x30: in nvbios_volt_table()
55 case 0x40: in nvbios_volt_table()
56 case 0x50: in nvbios_volt_table()
65 return 0; in nvbios_volt_table()
[all …]
/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c47 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
48 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
49 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
50 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
51 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
54 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
55 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
56 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
Dgfx_v8_0.c62 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
63 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
65 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
77 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
78 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
79 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
80 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
82 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
Dnvidia,tegra124-emc.yaml38 "^emc-timings-[0-9]+$":
48 "^timing-[0-9]+$":
79 minimum: 0
142 minimum: 0
340 reg = <0x70019000 0x1000>;
352 reg = <0x7001b000 0x1000>;
358 emc-timings-0 {
361 timing-0 {
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
/linux-5.10/drivers/net/wireless/ath/ath6kl/
Dtarget.h26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
[all …]
/linux-5.10/fs/unicode/
Dutf8-norm.c23 while (i >= 0 && utf8agetab[i] != 0) { in utf8version_is_supported()
28 return 0; in utf8version_is_supported()
45 * 0x00000000 0x0000007F: 0xxxxxxx
46 * 0x00000000 0x000007FF: 110xxxxx 10xxxxxx
47 * 0x00000000 0x0000FFFF: 1110xxxx 10xxxxxx 10xxxxxx
48 * 0x00000000 0x001FFFFF: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
49 * 0x00000000 0x03FFFFFF: 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
50 * 0x00000000 0x7FFFFFFF: 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
57 * 0x00000000 0x0000007F: 0xxxxxxx
58 * 0x00000080 0x000007FF: 110xxxxx 10xxxxxx
[all …]
Dmkutf8data.c50 int verbose = 0;
63 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
98 return 0; in age_valid()
100 return 0; in age_valid()
102 return 0; in age_valid()
119 * if offlen == 0 (non-branching node)
124 * if offlen != 0 (branching node)
133 #define BITNUM 0x07
134 #define NEXTBYTE 0x08
135 #define OFFLEN 0x30
[all …]
/linux-5.10/drivers/gpu/drm/savage/
Dsavage_drv.h101 S3_UNKNOWN = 0,
227 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
228 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
229 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
230 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
231 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
233 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
241 #define SAVAGE_STATUS_WORD0 0x48C00
242 #define SAVAGE_STATUS_WORD1 0x48C04
243 #define SAVAGE_ALT_STATUS_WORD0 0x48C60
[all …]
/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_irq_kms.c130 for (i = 0; i < RADEON_NUM_RINGS; i++) in radeon_driver_irq_preinstall_kms()
131 atomic_set(&rdev->irq.ring_int[i], 0); in radeon_driver_irq_preinstall_kms()
133 for (i = 0; i < RADEON_MAX_HPD_PINS; i++) in radeon_driver_irq_preinstall_kms()
135 for (i = 0; i < RADEON_MAX_CRTCS; i++) { in radeon_driver_irq_preinstall_kms()
137 atomic_set(&rdev->irq.pflip[i], 0); in radeon_driver_irq_preinstall_kms()
152 * Returns 0 on success.
159 dev->max_vblank_count = 0x00ffffff; in radeon_driver_irq_postinstall_kms()
161 dev->max_vblank_count = 0x001fffff; in radeon_driver_irq_postinstall_kms()
163 return 0; in radeon_driver_irq_postinstall_kms()
184 for (i = 0; i < RADEON_NUM_RINGS; i++) in radeon_driver_irq_uninstall_kms()
[all …]
/linux-5.10/drivers/net/ethernet/intel/fm10k/
Dfm10k_type.h16 #define FM10K_DEV_ID_PF 0x15A4
17 #define FM10K_DEV_ID_VF 0x15A5
18 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
19 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
25 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
26 #define FM10K_STAT_VALID 0x80000000
29 #define FM10K_PCIE_LINK_CAP 0x7C
30 #define FM10K_PCIE_LINK_STATUS 0x82
31 #define FM10K_PCIE_LINK_WIDTH 0x3F0
32 #define FM10K_PCIE_LINK_WIDTH_1 0x10
[all …]
/linux-5.10/drivers/parisc/
Dlba_pci.c101 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
107 #define LBA_FLAG_SKIP_PROBE 0x10
146 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
147 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
197 return 0; in lba_device_present()
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
280 #define LBA_MASTER_ABORT_ERROR 0xc
281 #define LBA_FATAL_ERROR 0x10
284 u32 error_status = 0; \
[all …]
/linux-5.10/drivers/net/ethernet/sfc/
Dsiena.c52 FRF_CZ_TC_TIMER_VAL, 0); in siena_push_irq_moderation()
60 if (efx->fc_disable++ == 0) in siena_prepare_flush()
66 if (--efx->fc_disable == 0) in siena_finish_flush()
72 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
74 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
76 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
78 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
80 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
82 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
84 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
[all …]
/linux-5.10/drivers/mmc/host/
Dau1xmmc.c60 #define DBG(fmt, idx, args...) do {} while (0)
67 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
68 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
78 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
125 #define HOST_F_XMIT 0x0001
126 #define HOST_F_RECV 0x0002
127 #define HOST_F_DMA 0x0010
128 #define HOST_F_DBDMA 0x0020
129 #define HOST_F_ACTIVE 0x0100
130 #define HOST_F_STOP 0x1000
[all …]
/linux-5.10/drivers/staging/media/hantro/
Drk3399_vpu_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]

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