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Searched +full:0 +full:x00000700 (Results 1 – 7 of 7) sorted by relevance

/qemu/hw/display/
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
[all …]
/qemu/hw/misc/
H A Deccmemctl.c35 * MCC (version 0, implementation 0) SS-600MP
36 * EMC (version 0, implementation 1) SS-10
37 * SMC (version 0, implementation 2) SS-10SX and SS-20
44 #define ECC_MCC 0x00000000
45 #define ECC_EMC 0x10000000
46 #define ECC_SMC 0x20000000
49 #define ECC_MER 0 /* Memory Enable Register */
53 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
56 #define ECC_ECR0 7 /* Event Count Register 0 */
60 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
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/qemu/target/ppc/
H A Dcpu_init.c71 0x00000000); in register_745_sprs()
75 0x00000000); in register_745_sprs()
79 0x00000000); in register_745_sprs()
83 0x00000000); in register_745_sprs()
89 0x00000000); in register_745_sprs()
94 0x00000000); in register_745_sprs()
99 0x00000000); in register_745_sprs()
108 0x00000000); in register_755_sprs()
113 0x00000000); in register_755_sprs()
123 KVM_REG_PPC_DABR, 0x00000000); in register_7xx_sprs()
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/qemu/hw/net/
H A Dxgmac.c39 } while (0)
41 #define DEBUGF_BRK(message, args...) do { } while (0)
44 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
45 #define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */
46 #define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */
47 #define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */
48 #define XGMAC_VERSION 0x00000008 /* Version */
50 #define XGMAC_VLAN_INCL 0x00000009
51 #define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */
52 #define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */
[all …]
/qemu/hw/scsi/
H A Dmpi.h37 MPI_FUNCTION_SCSI_IO_REQUEST = 0x00,
38 MPI_FUNCTION_SCSI_TASK_MGMT = 0x01,
39 MPI_FUNCTION_IOC_INIT = 0x02,
40 MPI_FUNCTION_IOC_FACTS = 0x03,
41 MPI_FUNCTION_CONFIG = 0x04,
42 MPI_FUNCTION_PORT_FACTS = 0x05,
43 MPI_FUNCTION_PORT_ENABLE = 0x06,
44 MPI_FUNCTION_EVENT_NOTIFICATION = 0x07,
45 MPI_FUNCTION_EVENT_ACK = 0x08,
46 MPI_FUNCTION_FW_DOWNLOAD = 0x09,
[all …]
/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
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/qemu/hw/arm/
H A Daspeed.c60 /* Palmetto hardware value: 0x120CE416 */
98 /* AST2500 evb hardware value: 0xF100C2E6 */
109 /* Romulus hardware value: 0xF10AD206 */
119 /* Sonorapass hardware value: 0xF100D216 */
148 /* FP5280G2 hardware value: 0XF100D286 */
163 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
180 #define AST2600_EVB_HW_STRAP1 0x000000C0
181 #define AST2600_EVB_HW_STRAP2 0x00000003
186 #define AST2700_EVB_HW_STRAP1 0x00000800
188 #define AST2700_EVB_HW_STRAP2 0x00000700
[all …]